Efficient fir filter for high-speed communication

Details Efficient fir filter for high-speed communication Efficient fir filter for high-speed communication

1999-11-09

2001-08-07

Chin, Stephen (Department: 2634)

Pulse or digital communications

Equalizers

C375S233000, C375S350000, C708S319000

Reexamination Certificate

active

06272173

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods and systems for increasing efficiency of a filter in a communication system. More particularly, the invention relates to a method and a system for reducing propagation delay and power consumption of a finite impulse response (FIR) filter in a high-speed communication system.
2. Description of Related Art
In a Gigabit Ethernet communication system that conforms to the IEEE 802.3ab (also termed 1000BASE-T) standard, gigabit transceivers are connected via four Category 5 twisted pairs of copper cables. Symbol data are transmitted at the rate of 250 megabits per second (Mbps) on each twisted pair of copper cable.
A Gigabit Ethernet transceiver includes a larger number of digital filters, which in turn require a large number of registers. The registers operate at the clock rate of 125 megahertz (MHz) and have large number of taps. If the propagation delay of a filter exceeds the clock period then the filter is not useable.
Thus, there is a need for an efficient digital filter for use in a high speed communication system.
SUMMARY OF THE INVENTION
The present invention provides a method for reducing a propagation delay of a digital filter. The digital filter has an input path and an output path and includes a set of delay elements and a number of taps. The taps couples the input path to the output path. Each of the taps includes a coefficient, a multiplier and an adder. Each of the delay elements is disposed between two adjacent taps. The delay elements are placed in both the input path and the output path of the digital filter, such that the digital filter has fewer delay elements in the input path than a direct-form digital filter having the same number of taps in a direct-form structure and has fewer delay elements in the output path than a transposed-form digital filter having the same number of taps in a transposed-form structure, and such that the digital filter has same transfer function as the direct-form digital filter and the transposed-form digital filter.


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patent: WO 98/43369 (1998-10-01), None
Duncan et al.: “Strategies for design automation of high speed digital filters” Journal of VLSI Signal Processing, vol. 9, No. ½, Sep. 1995 pp. 105-118, XP000525889, Dordrecht, NL.
Caraiscos, Pekmestzi: “Low-latency bit-parallel systolic VLSI implementation of FIR digital filters” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, No. 7, Jul. 1996, pp. 529-534, XP000630793 New York, US, ISSN: 1057-7130.
Pekmestzi, Caraiscos: “Implementation of systolic multipliers and digital filters via signal flow-graph transformations” The Mediterranean Electrotechnical Conference, Apr. 12-14, 1994, pp. 105-108, XP000506110, New York, US ISBN: 0-7803-1773-4.
Level One Communications, Inc., Combined Parallel Adaptive Equalizer/Echo Canceller, WO 98/43369 A, International Publication Date Oct. 1, 1998.
IEEE Std 802.3ab-1999 (Supplement to IEEE Std 802.3, 1998 Edition), entitled Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications—Physical Layer Parameters and Specifications for 1000 Mb/s Operation Over 4-Pair of Category 5 Balanced Copper Cabling, Type 1000BASE-T.
Mehdi Hatamian et al., Design Considerations for Gigabit Ethernet 100Base-T Twisted Pair Transceivers, IEEE 1998 Custom Integrated Circuits Conference, 15.1.1-15.1.8.

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