Efficient filtering of RxLOS signal in SerDes applications

Details Efficient filtering of RxLOS signal in SerDes applications Efficient filtering of RxLOS signal in SerDes applications

2007-08-21

2007-08-21

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Receivers

Interference or noise reduction

C375S376000, C375S359000, C375S361000, C327S034000, C327S552000, C235S440000, C377S111000

Reexamination Certificate

active

10444697

ABSTRACT:
An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may be prevented from affecting the whole clock cycle. The false signal removal circuitry is effective against both false active high and false active low signals. A selectable majority determination block also measures the number of glitches or average signal strength to determine that a valid signal is present. A mininum pulse width of a glitch is settable.

REFERENCES:
patent: 4775840 (1988-10-01), Ohmori et al.
patent: 5001374 (1991-03-01), Chang
patent: 5770846 (1998-06-01), Mos et al.
patent: 6026141 (2000-02-01), Lo
patent: 6914951 (2005-07-01), Erickson et al.
patent: 7003066 (2006-02-01), Davies et al.

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