Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-08-12
2002-04-23
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C375S295000
Reexamination Certificate
active
06377967
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a method and apparatus which provide a low cost digital filter that performs a continuous real time output programmable filter function.
2. Description of the Related Art
FIG. 1
a
shows a generic structure
10
for all filters. This structure
10
consists of a combination of delay elements
12
, adders
14
and multipliers
16
. The delay elements
12
are positioned between adders
14
. In the generic structure shown, the multipliers
16
form both a feed forward path
18
and a feedback path
20
are illustrated.
In the feed forward path
18
, the input signal is delivered to a plurality of multipliers
16
, where the input signal is multiplied by a weight. The input signal is also delivered to a delay element
12
, and then to the adder
14
, which outputs the sum of the weighted signal and the delayed signal.
In the feedback path
20
, the output signal is delivered to another plurality of multipliers
16
, where the output signal is multiplied by a weight. The weighted output signal is then delivered to an adder
14
, which outputs the sum of the weighted signal and the delayed signal.
One common type of digital filter which uses the generic structure shown in
FIG. 1
a
is a finite-impulse-response (FIR) filter, shown in
FIG. 1
b.
The FIR filter only used the feed forward path
18
shown in
FIG. 1
a.
The delay elements
12
are replaced with a digital tapped delay line
22
. This results in a moving average which is non-recursive.
For typical electronic warfare (EW) applications, the FIR filter will be designed with 30 to 40 taps. The FIR filter is programmed, i.e., appropriately and individually adjusting the weights of these taps. This programming involves controlling the three key filter parameters, i.e., the center frequency, the bandwidth, and the shape factor.
Cost of a digital filter is linearly dependent on the number of multiplies required. Multiplying takes far more hardware than adding or delaying. A digital filter requires many multiplies to individually adjust the tap weights, although this can be reduced by half.
An infinite-impulse-response (IIR) filter uses weighted feedback paths, instead of the weighted feed forward paths of the FIR filter, to form a recursive difference filter. Using feedback requires fewer paths, typically called poles rather than taps, with a five pole filter being typical for EW applications. Thus, the IIR digital filter needs fewer multiplies.
However, the IIR filter also has a different phase response, which is undesirable for some applications. Further, the reduction in hardware is still not sufficient. For either of these filters, at either each tap or pole, the signal will be multiplied by a weighting coefficient, the sequence of which represent a desired filter response.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method and an apparatus for reducing internal operations, especially the number of multiplies, required by a digital filter. This reduction will result in a decreased cost of the digital filter.
These and other objects of the present invention will become more readily apparent from detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein;
FIG. 1
a
illustrates a generic digital filter structure;
FIG. 1
b
is a conventional FIR digital filter;
FIG. 2
is a digital filter according to the present invention;
FIG. 3
a
is an embodiment of a summing circuit of the present invention;
FIG. 3
b
is another embodiment of the summing circuit of the present invention;
FIG. 3
c
is yet another embodiment of the summing circuit of the present invention; and
FIG. 4
is a schematic of a memory of the present invention to be used with the digital filter of the present invention and is often referred to as a digital radio frequency memory (DRFM).
REFERENCES:
patent: 4606009 (1986-08-01), Wiesmann
patent: 5068818 (1991-11-01), Uramoto et al.
patent: 5448508 (1995-09-01), Ono et al.
patent: 5568507 (1996-10-01), Hershey et al.
patent: 5677932 (1997-10-01), Comte et al.
patent: 5812605 (1998-09-01), Smith et al.
patent: 6081822 (2000-06-01), Hillery et al.
patent: 6091780 (2000-07-01), Sointula
patent: 6141542 (2000-10-01), Kotzin et al.
patent: 6173014 (2001-01-01), Forssen et al.
Mai Tan V.
Northrop Grumman Corporation
LandOfFree
Efficient digital integration technique filter does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Efficient digital integration technique filter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient digital integration technique filter will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2911020