Efficient computation of the modulo operation based on...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

07849125

ABSTRACT:
A system and method for computing A mod (2n−1), where A is an m bit quantity, where n is a positive integer, where m is greater than or equal to n. The quantity A may be partitioned into a plurality of sections, each being at most n bits long. The value A mod (2n−1) may be computed by adding the sections in mod(2n−1) fashion. This addition of the sections of A may be performed in a single clock cycle using an adder tree, or, sequentially in multiple clock cycles using a two-input adder circuit provided the output of the adder circuit is coupled to one of the two inputs. The computation A mod (2n−1) may be performed as a part of an interleaving/deinterleaving operation, or, as part of an encryption/decryption operation.

REFERENCES:
patent: 4598266 (1986-07-01), Bernardson
patent: 4658094 (1987-04-01), Clark
patent: 4686510 (1987-08-01), Baker
patent: 4722067 (1988-01-01), Williams
patent: 4742479 (1988-05-01), Kloker et al.
patent: 4742520 (1988-05-01), Hoac et al.
patent: 4800524 (1989-01-01), Roesgen
patent: 4833602 (1989-05-01), Levy et al.
patent: 4870607 (1989-09-01), Ishizuka
patent: 4891781 (1990-01-01), Omura
patent: 4935867 (1990-06-01), Wang et al.
patent: 4994994 (1991-02-01), Burgess et al.
patent: 5008849 (1991-04-01), Burgess et al.
patent: 5038376 (1991-08-01), Mittenthal
patent: 5210710 (1993-05-01), Omura
patent: 5233553 (1993-08-01), Shak et al.
patent: 5249148 (1993-09-01), Catherwood et al.
patent: 5257272 (1993-10-01), Fredrickson
patent: 5289397 (1994-02-01), Clark et al.
patent: 5345410 (1994-09-01), Yokoyama et al.
patent: 5381360 (1995-01-01), Shridhar et al.
patent: 5384810 (1995-01-01), Amrany
patent: 5414651 (1995-05-01), Kessels
patent: 5440705 (1995-08-01), Wang et al.
patent: 5479511 (1995-12-01), Naccache
patent: 5493522 (1996-02-01), Rosenberg
patent: 5572454 (1996-11-01), Lee et al.
patent: 5606520 (1997-02-01), Gove et al.
patent: 5633814 (1997-05-01), Palaniswami
patent: 5649146 (1997-07-01), Riou
patent: 5659700 (1997-08-01), Chen et al.
patent: 5664193 (1997-09-01), Tirumalai
patent: 5719798 (1998-02-01), Lutz et al.
patent: 5790443 (1998-08-01), Shen et al.
patent: 5793660 (1998-08-01), Rentschler
patent: 5794025 (1998-08-01), Bergantino et al.
patent: 5809308 (1998-09-01), Tirumalai
patent: 5867711 (1999-02-01), Subramanian et al.
patent: 5905665 (1999-05-01), Rim
patent: 5918252 (1999-06-01), Chen et al.
patent: 5940863 (1999-08-01), Fimoff et al.
patent: 5982900 (1999-11-01), Ebihara et al.
patent: 6038318 (2000-03-01), Roden
patent: 6047364 (2000-04-01), Kolagotla et al.
patent: 6049858 (2000-04-01), Kolagotla et al.
patent: 6052768 (2000-04-01), Rim
patent: 6064740 (2000-05-01), Curiger et al.
patent: 6073228 (2000-06-01), Holmqvist et al.
patent: 6182104 (2001-01-01), Foster et al.
patent: 6282255 (2001-08-01), La Rosa et al.
patent: 6304398 (2001-10-01), Gaub et al.
patent: 6321247 (2001-11-01), Matthews et al.
patent: 6341370 (2002-01-01), Tirumalai et al.
patent: 6448915 (2002-09-01), Logue
patent: 6536001 (2003-03-01), Cai et al.
patent: 6584556 (2003-06-01), Witt
patent: 6591213 (2003-07-01), Burlison
patent: 6604169 (2003-08-01), Catherwood
patent: 6634024 (2003-10-01), Tirumalai et al.
patent: 6651247 (2003-11-01), Srinivasan
patent: 6671878 (2003-12-01), Bliss
patent: 6707627 (2004-03-01), Reed et al.
patent: 6728743 (2004-04-01), Shachar
patent: 6832370 (2004-12-01), Srinivasan et al.
patent: 6839648 (2005-01-01), Burlison
patent: 6900910 (2005-05-01), Ganapahti et al.
patent: 6963645 (2005-11-01), Chen et al.
patent: 6973470 (2005-12-01), Takahashi et al.
patent: 6986131 (2006-01-01), Thompson et al.
patent: 6993757 (2006-01-01), Rajagopalan
patent: 2002/0007484 (2002-01-01), Tirumalai et al.
patent: 2002/0124039 (2002-09-01), Inoue et al.
patent: 2002/0129074 (2002-09-01), Shachar
patent: 2002/0194237 (2002-12-01), Takahashi et al.
patent: 2002/0194452 (2002-12-01), Catherwood
patent: 2003/0031316 (2003-02-01), Langston et al.
patent: 2003/0056080 (2003-03-01), Watanabe
patent: 2003/0065697 (2003-04-01), Patel et al.
patent: 2003/0074382 (2003-04-01), Schmandt et al.
patent: 2003/0112969 (2003-06-01), Algesheimer et al.
patent: 2003/0208749 (2003-11-01), Rajagopalan
patent: 2003/0225958 (2003-12-01), Efland et al.
patent: 2003/0233643 (2003-12-01), Thompson et al.
patent: 2004/0003022 (2004-01-01), Garrison et al.
patent: 2004/0003340 (2004-01-01), Chen et al.
patent: 2004/0083251 (2004-04-01), Geiringer et al.
patent: 2004/0128339 (2004-07-01), Kalampoukas et al.
patent: 2004/0199560 (2004-10-01), Dupaquis et al.
patent: 2004/0221283 (2004-11-01), Worley
patent: 2004/0268335 (2004-12-01), Martin et al.
patent: 2005/0004967 (2005-01-01), Becker
patent: 2005/0027776 (2005-02-01), Lou
patent: 2005/0185791 (2005-08-01), Chen et al.
patent: 2005/0223052 (2005-10-01), Schimmler et al.
patent: 2005/0256996 (2005-11-01), Watanabe
patent: 2005/0278572 (2005-12-01), Busaba et al.
patent: 2006/0010191 (2006-01-01), Takahashi et al.
patent: 2006/0015553 (2006-01-01), Takahashi et al.
patent: 2006/0045263 (2006-03-01), Brokenshire et al.
patent: 2006/0048123 (2006-03-01), Martin
patent: 2006/0048124 (2006-03-01), Martin
patent: 0318957 (1989-06-01), None
patent: 2786579 (2000-06-01), None
Reto Zimmermann. “Efficient VLSI Implementation of Modulo (2″+1) Addition and Multiplication.” Swiss Federal Institute of Technology (ETH). Integrated Systems Laboratory, CH-8092 Zurich, Switzerland.
Parhami, Behrooz. “Computer Arithmetic: Algorithms and Hardware Designs.” Oxford University Press. Jul. 2, 2000. pp. 125-128.
Ranada, Abhiram G. et al. “Interconnection Networks and Parallel Memory Organizations for Array Processing.” Proceedings of the International Conference on Parallel Processing. Aug. 20-23, 1985. Washington, IEEE Comp. Soc Press, US, pp. 41-47. XP000757117.
Sivakumar, R. et al. “VLSI Design of a Modulo-Extractor.” Communications, Computers and Signal Processing. 1991. IEEE Pacific Rim Conference on Victoria, BC, Canada. May 9-10, 1991. pp. 327-330. XP010039443. ISBN: 0-87942-638-1.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Efficient computation of the modulo operation based on... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient computation of the modulo operation based on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient computation of the modulo operation based on... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4154701

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.