Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2011-06-14
2011-06-14
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C712S221000
Reexamination Certificate
active
07962719
ABSTRACT:
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.
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Pitsianis et al., “High-performance FFT Implementation of the BOPS ManArray Paralel DSP”, SPIE Conference on Advanced Signal Processing Algorithms, Architectures, and Impelemntations IX, Denver, Colorado, Jul. 1999, SPIE vol. 3807, pp. 164-169.
Pechanek Gerald George
Pitsianis Nikos P.
Rodriguez Ricardo
Pan Daniel
Priest & Goldstein PLLC
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