Efficient architecture for correcting component mismatches and c

Details Efficient architecture for correcting component mismatches and c Efficient architecture for correcting component mismatches and c

1996-06-12

1997-06-10

DeBoer, Todd

Coded data generation or conversion

Converter compensation

341120, H03M 106

Patent

active

056380712

ABSTRACT:
An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.

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