Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-12-09
2001-07-10
Ngo, Chuong Dinh (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S319000
Reexamination Certificate
active
06260053
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to signal processing systems. More specifically, the invention relates to filtering systems for usage in various applications including decimators.
2. Description of the Related Art
Signal processing systems often include digital filters for performing various filtering operations. Digital filters are classified into two types, infinite impulse response (IIR) filters and finite impulse response (FIR) filters. FIR filters are commonly used to perform digital filtering functions. For causal systems with finite-duration impulse responses, filters generally process an input signal according to a nonrecursive computational algorithm.
Accordingly, digital filters generally perform a large number of computations (e.g., multiplication) and require a large number of storage elements (e.g., registers) for temporarily storing computed variables (e.g., state variables) in carrying out the computations. The number of storage elements and computations carried out by a digital filter directly effects the device's size, speed, and power consumption. As the complexity of digital filters increase, the number of computation and the number of registers required tend to increase. At the same time, improved performance is continually expected from digital filters.
For these reasons, it is desirable to improve the computational efficiency and speed (e.g., reduce the number of computations) and reduce the number of storage elements required in FIR filters. It is also desirable to have a scalable filter architecture that can accommodate different complexity levels and be capable of achieving the required performance.
SUMMARY OF THE INVENTION
The present invention provides a method, apparatus, and system to provide a filter architecture that is computationally efficient, requires fewer storage elements, and is scalable to accommodate different complexity levels while still achieving the required performance.
The present invention meets the above need with a scalable Finite Impulse Response (FIR) filter comprising at least one linear-phase decimation-by-2 processing element. The FIR filter can provide scalable processing capability by connecting a plurality of substantially similar linear-phase decimation-by-2 processing elements together in series such that the substantially similar processing elements are configurable to operate independently and in parallel. Each processing element is in transpose form. Each processing element utilizes coefficient symmetry to reduce the number of multiplication operations. Each processing element utilizes the transpose form to reduce the number of state variable storage elements. Each processing element has a first and second sets of predetermined coefficients.
Under the present invention, the configuration and interconnection between the processing elements are as follows. The first processing element in the series computes a first value based on the first set of predetermined coefficients of the first processing element and the samples of the input signal. If the first processing element is connected to a subsequent neighbor processing element, the first processing element provides the first value to the subsequent neighbor processing element and receives a second value from the subsequent neighbor processing element. The first processing element computes a third value based on the second value, the second set of predetermined coefficients of the first processing element, and the samples of the input signal. If the first processing element is not connected to a subsequent neighbor processing element, the first processing element computes the third value based on the first value, the second set of predetermined coefficients of the first processing element, and the samples of the input signal. The subsequent neighbor processing element computes a fourth value based on the first value received from the first processing element, a first set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal. If the subsequent neighbor processing element is connected to another subsequent neighbor processing element, the subsequent neighbor processing element provides the fourth value to the another subsequent neighbor processing element and receives a fifth value from the another subsequent neighbor processing element. The subsequent neighbor processing element computes the second value based on the fifth value, a second set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal. If the subsequent neighbor processing element is not connected to the another subsequent neighbor processing element, the subsequent neighbor processing element computes the second value based on the fourth value, a second set of predetermined coefficients of the subsequent neighbor processing element, and the samples of the input signal. The scalable filter architecture in accordance with the present invention may include a large number of processing elements.
All the features and advantages of the present invention will become apparent from the following detailed description of its preferred embodiment whose description should be taken in conjunction with the accompanying drawings.
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Kan Zhao
Mandeep Chadha S.
Maulik Prabir C.
Cirrus Logic Inc.
Koestner Ken J.
Ngo Chuong Dinh
Skjerven Morrill Macpherson
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