Efficiency charge pump circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S537000, C363S059000

Reexamination Certificate

active

06448841

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
BACKGROUND OF THE INVENTION
Charge pumps are known in the art. A charge pump comprises a series of charge storage and transfer elements coupled together which increase the output voltage by a quantity of approximately 1*Vin. The charge storage elements are coupled from one stage to the next by the transfer element such as PMOS switches. A major source of current drain internal to the charge pump can be forward biasing of the gate-well diode of the PMOS switches during the charging and transfer cycles. In a standard N-Well CMOS process, PMOS transistors are fabricated in N-type wells in a P-type substrate. PMOS transistors could perform the switching functions, but parasitic PNP bipolar transistors formed by the P+source/N-Well/P-substrate and the P+drain/N-Well/P-substrate can bleed charge into the P-substrate faster than it can be put into the pump. If this happens it will render the charge pump useless. It would be desirable to reduce the current drain resulting from the forward biasing of the gate-well diode of the PMOS switches in order to improve the efficiency of the charge pump.
BRIEF SUMMARY OF THE INVENTION
The present invention utilizes a plurality of transistors configured such that the gate-well diode of the PMOS switch is not forward biased during any part of the charge pump cycle. In one embodiment the plurality of transistors are coupled between the drain, source and well of the PMOS switch such that the well of the PMOS switch is connected to a voltage that is one base-emitter voltage drop (Vbe) less than the higher of either the source voltage or the drain voltage. Since the well is always a single Vbe below the higher of the source voltage or the drain voltage, the gate-well diodes of the PMOS switches are prevented from becoming forward biased, thereby reducing current drain and resulting in improved efficiency of the charge pump. A further embodiment utilizes a plurality of switches and a specific switching sequence such that certain switches at a first side of the pump capacitors are allowed to float while certain switches at the second side of the pump capacitors are being configured, then once the switches at the second side of the pump capacitors are configured, the switches at the first side of the pump capacitors are used to transfer the charge from one capacitor to another. Accordingly, the drain-well diode of the PMOS switches are not forward biased during the charge pump cycles.


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