Effective use of memory bus in a multiprocessing environment by

Details Effective use of memory bus in a multiprocessing environment by Effective use of memory bus in a multiprocessing environment by

1995-06-06

1996-12-17

Rudolph, Rebecca L.

Boots, shoes, and leggings

395460, 395457, 395471, 364DIG1, G06F 1208

Patent

active

055862985

ABSTRACT:
A cache control circuit reduces the number of accesses to main memory in a multiprocessing system. The circuit allows a cache memory associated with one Central Processing Unit (CPU) to recognize and respond to memory requests from another CPU, and includes specialized circuitry to support burst-mode operations. Data in one cache memory may be transferred to another cache without the need to access main memory. The direct transfer of requested data between caches in a multiprocessor system results in providing the requested data quickly and also reduces the traffic in the memory bus. By transaction duration can further be reduced by making the snooping cache smarter.

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Prete, "RST Cache Memory Design For A Tightly Coupled Multiprocessor System", IEEE Micro, vol. 11:16-52, (1991).

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