Eeprom write device

Details Eeprom write device Eeprom write device

2000-05-01

2001-07-03

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S189011, C365S191000

Reexamination Certificate

active

06256226

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an EEPROM write device which rewrites an EEPROM such as a flash memory installed in, for example, an ECU (electronic control unit) of a vehicle according to a serial signal from the external, and more particularly to an EEPROM write device which is adapted to be automatically writable at the ECU side according to an input of only the serial signal from an external write device and simplifies a communication terminal structure between the external write device and the ECU and a circuit structure thereof.
2. Description of the Related Art
Up to now, an ECU mounted on a vehicle stores various program for vehicle control therein. Also, the contents of control program are written in an EEPROM from which data may be electrically erased and into which data may be rewritten, and are appropriately rewritten by connection to the external write device if necessary, as disclosed, for example, in Japanese Patent Application Laid-open No. Sho 63-223901 (Patent No. 2753225).
In general, the write processing of the EEPROM is implemented by supplying a write enable signal to an IC circuit containing the EEPROM and supplying address data and memory data after the IC circuit is switched to a write mode.
FIG. 5
is a block diagram showing the structure of a conventional EEPROM write device using an external write device.
Referring to
FIG. 5
, an external write device
1
is connected to an ECU
2
mounted on a vehicle when a write processing is conducted and produces a write enable signal WA and a serial signal SE.
The ECU
2
includes input terminal
21
and
22
as well as an output terminal
23
for connection to the external write device
1
so as to input the write enable signal WA and the serial signal SE through the input terminals
21
and
22
and output a serial signal SR to the external write device
1
through the output terminal
23
.
The ECU
2
includes a microcomputer
3
which constitutes a control processing unit, a write control circuit
4
associated with the microcomputer
3
, a reset pulse generating circuit
5
, a CPU operation monitoring circuit
6
, a communication circuit
7
and a gate circuit
8
.
The microcomputer
3
includes a CPU
30
that constitutes a microcomputer main body, an EEPROM
31
such as a flash memory belonging to the CPU
30
, a boot program
32
and a RAM
33
.
Hereinafter, a description will be given of an example in which the flash memory
31
is employed as the EEPROM.
The boot program
32
stores a start program for write preparation or the like therein, and the flash memory
31
stores a sequence program of the CPU
30
and other programs therein.
The write control circuit
4
converts the write enable signal WA supplied from the external write device
1
into a write mode set signal WM and inputs the signal WM to the CPU
30
within the microcomputer
3
.
The write mode set signal WM conducts write enablement and the decision of the operation mode which are necessary for the microcomputer
3
.
The reset pulse generating circuit
5
generates a reset pulse RS for the CPU
30
within the microcomputer
3
in response to the write enable signal WA supplied from the external write device
1
.
The CPU operation monitoring circuit
6
generates the reset pulse RS in response to the presence/absence of a watchdog signal which is periodically supplied from the CPU
30
within the microcomputer
3
.
The communication circuit
7
conducts bidirectional communication of the serial signals SE and SR between the external write device
1
and the microcomputer
3
.
The gate circuit
8
allows the reset pulse RS to pass and inputs it to the CPU
30
so as to give preference to the reset pulse RS from the reset pulse generating circuit
5
rather than the reset pulse RS from the CPU operation monitoring circuit
6
.
Subsequently, a description will be given of the operation of the conventional EEPROM write device shown in
FIG. 5
with reference to
FIG. 6
(normal operation) and a flowchart of
FIG. 7
(write interrupt).
It is assumed that arbitrary system control program is written in a flash memory
31
within the microcomputer
3
.
Referring to
FIG. 6
, when the ECU
2
and the microcomputer
3
are first operated upon turning on a power (step S
1
), a normal control program starts, and the ECU
2
and the microcomputer
3
are operated according to the normal system control program (step S
2
).
When the write enable signal WA is supplied from the external write device
1
, write interrupt (see
FIG. 7
) takes place, and when write interrupt is completed, processing is returned to a processing routine shown in FIG.
6
. Then, the power is turned off (step S
20
) to end the normal processing shown in FIG.
6
.
Referring to
FIG. 7
, the write control circuit
4
first generates the write mode set signal WM for write enable and operation mode setting of the microcomputer
3
in response to the write enable signal WA (step S
3
). In response to the signal WM, the microcomputer
3
executes the switching processing to the write mode (step S
4
).
Also, while the write enable signal WA is supplied, the reset pulse generating circuit
5
supplies the reset pulse RS to the microcomputer
3
(step S
5
) to stop the watchdog signal WD (step S
6
).
After completion of the above processing steps S
3
to S
6
, the reset pulse generating circuit
5
stops the supply of the reset pulse RS to the microcomputer
3
(step S
7
). As a result, the microcomputer
3
makes a transition to the operation at the write mode, and the contents of the built-in boot program
32
are transferred and start (step S
8
).
After the boot program
32
starts, the external write device
1
and the microcomputer
3
start data write processing in the flash memory
31
based on the serial signal SE through communication of the serial signals SE and SR (step S
9
).
Then, it is judged whether an input of the serial signal SE (write processing) is completed, or not (step S
10
), and if it is judged that the write processing is completed (that is, YES), the external write device
1
stops the supply of the write enable signal WA in response to the serial signal SR from the CPU
30
which is indicative of the completion of the write processing (step S
11
).
As a result, the microcomputer
3
executes the switching processing to the normal operation mode (step S
12
).
At the same time, the CPU operation monitoring circuit
6
inputs the reset pulse RS to the CPU
30
through the gate circuit
8
(step S
13
).
In other words, the reset control operation by the reset pulse generating circuit
5
stops, and the reset pulse RS from the CPU operation monitoring circuit
6
is supplied to the microcomputer
3
.
After the completion of the above processing steps S
11
to S
13
, the reset pulse generating circuit
5
stops the supply of the reset pulse RS to the microcomputer
3
(step S
14
).
As a result, the processing routine shown in
FIG. 7
is completed, and the normal system control program (see
FIG. 6
) starts, and processing is returned to the original operation of the ECU
2
.
As described above, upon stopping the supply of the write enable signal WA at the time of completing write operation, the write mode is cancelled in the microcomputer
3
to switch to the operation mode using the normal system control program (step S
2
).
However, the above conventional device requires the input terminal
21
for transmitting the write enable signal WA from the external write device
1
to the ECU
2
as a structure not involved in the normal control operation but involved only in the data write operation.
Also, although not shown in
FIG. 5
, it is necessary to provide not only an exclusive input/output terminal for the write enable signal WA but also a wire (harness) connecting the external write device
1
and the ECU
2
to each other therebetween.
As described above, in the conventional EEPROM write device, it is necessary to transmit the exclusive write enable signal WA from the external write device
1
to the EC

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