EEPROM with improved erase structure

Details EEPROM with improved erase structure EEPROM with improved erase structure

1988-05-03

1991-03-05

Gossage, Glenn

Static information storage and retrieval

Floating gate

Particular biasing

365 51, 365218, 357 235, G11C 1604

Patent

active

049982206

ABSTRACT:
An electrically erasable programmable read only memory (EEPROM) constructed in accordance with the invention includes a source, a drain, a channel region formed between the source and drain, a floating gate extending over a first portion of the channel region but not a second portion of the channel region, and a control gate extending over a first portion of the floating gate and the second portion of the channel region. Of importance, the EEPROM includes an erase gate which is formed concurrently with the control gate and extending over a second portion of the floating gate. Because the erase gate is formed concurrently with the control gate, the process used to form the EEPROM requires only two layers of polysilicon. Also, because electrons tunnel between the floating gate and the erase gate during electrical erase instead of between the floating gate and the drain, there is no PN junction breakdown during electrical erase and therefore, the EEPROM array can be erased using a low current voltage supply.

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"An In-System Reprogrammable 256K CMOS Flash Memory," by Kynett et al., IEEE International Solid-State Circuits Conference, Feb. 18, 1988, pp. 132-133,330.
"Analysis and Modeling of Floating Gate EEPROM Cells," by Kolodny et al., IEEE Transactions on Electron Devices, vol. ED-33, No. 6, pp. 835-844, published in Jun. 1986.
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