EEPROM with improved circuit performance and reduced cell size

Details EEPROM with improved circuit performance and reduced cell size EEPROM with improved circuit performance and reduced cell size

2005-11-08

2005-11-08

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185050, C365S185260

Reexamination Certificate

active

06963503

ABSTRACT:
An EEPROM cell with reduced cell size and improved circuit performance includes a high-voltage (HV) capacitor, a low-voltage (LV) read path, and an HV write path, wherein either the HV capacitor is placed between the LV read path and the HV write path or the HV write path is placed between the LV read path and the HV capacitor. The EEPROM cell also includes a native floating-gate (FG) transistor in the LV read path. Using a native FG transistor in the LV read path results in further reduction in the cell size and improved circuit performance of the EEPROM cell.

REFERENCES:
patent: 5969992 (1999-10-01), Mehta et al.
patent: 6515899 (2003-02-01), Tu et al.

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