EEPROM verification circuit with PMOS transistors

Details EEPROM verification circuit with PMOS transistors EEPROM verification circuit with PMOS transistors

1994-10-28

1996-08-27

Beausoliel, Jr., Robert W.

Excavating

371 211, 36518522, 365201, G11C 2900

Patent

active

055508421

ABSTRACT:
The present invention provides a verification circuit for EEPROM cells by connecting PMOS verify transistors in parallel across the EEPROM cells to be tested. This configuration occupies less space on a PLD chip than prior verification circuits and allows all EEPROM bits associated with one logic cell in the PLD to be coupled to one verify path, minimizing logic complexity.

REFERENCES:
patent: 4937830 (1990-06-01), Kawashima et al.
patent: 5347490 (1994-09-01), Terada et al.

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