EEPROM using a merged source and control gate

Details EEPROM using a merged source and control gate EEPROM using a merged source and control gate

1988-11-15

1990-05-08

James, Andrew J.

357 236, 357 2311, 357 41, 357 54, H01L 2978, H01L 2702, H01L 2934

Patent

active

049242784

ABSTRACT:
A single layer of polycrystalline silicon (poly-Si) is used in an EEPROM structure, which obviates the need to form a separate control gate and floating gate. The EEPROM utilizes three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. A thin tunnel oxide layer separates the N+ source region of the write transistor from an N doped poly-Si layer and capacitively couples the source region to the poly-Si layer. The poly-Si layer extends over the N+ source region of the sense transistor and is capacitively coupled to the source region of the sense transistor via a thin gate oxide insulating layer which is thicker than the oxide layer comprising the tunnel oxide layer. This poly-Si layer continues to extend over a channel region separating the N+ source and N+ drain regions of the sense transistor, the poly-Si layer being separated from the channel via the thin gate oxide insulating layer. The drain of the sense transistor also acts as the source of the read transistor. In the above structure, the poly-Si layer acts as the floating gate over the channel of the sense transistor. Since the poly-Si floating gate is both capacitively coupled to the source of the sense transistor and to the source of the write transistor, no separate control gate or control gate electrode is needed (the source of the sense transistor acts as the control gate). The structure, inter alia, enables a higher coupling ratio during erasing, thus allowing faster erase times by coupling a higher voltage onto the poly-Si floating gate.

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Roger Cuppens et al., "An EEPROM for Microprocessors and Custom Logic", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 2, Apr. 1985, 603-608.
Jun-Ichi Miyamoto et al., "An Experimental 5-V-Only 256-kbit CMOS EEPROM with a High-Performance Single-Polysilicon Cell", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 852-859.

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