EEPROM semiconductor device and method of fabricating the same

Details EEPROM semiconductor device and method of fabricating the same EEPROM semiconductor device and method of fabricating the same

1998-07-30

2000-09-05

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257315, 257390, 257920, H01L 2348

Patent

active

061147672

ABSTRACT:
There is provided an EEPROM semiconductor device including (a) a plurality of field insulating films each extending perpendicularly to word lines, (b) a plurality of memory cells arranged in a matrix, each memory cell having a floating gate, a control gate formed on the floating gate and doubling as a word line, and source and drain regions located at either sides of the control gate, (c) a common source line extending in parallel with the word lines and connecting source regions of the memory cells with each other, and (d) a first bit line extending perpendicularly to the word lines and connecting drain regions of the memory cells with each other. The above-mentioned EEPROM semiconductor device makes it possible to form CMOS logic circuit together with a non-volatile memory on a common semiconductor substrate without increasing fabrication steps, and also makes it possible for the non-volatile memory to write data thereinto and read data therefrom at a higher rate without an increase in a cell size.

REFERENCES:
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5717635 (1998-02-01), Akatsu
patent: 5834807 (1998-11-01), Kim
patent: 5838615 (1998-11-01), Kimaya et al.

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