EEPROM memory protected against the effects from a breakdown...

Details EEPROM memory protected against the effects from a breakdown... EEPROM memory protected against the effects from a breakdown...

2005-08-23

2005-08-23

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185230, C365S185330, C365S185260

Reexamination Certificate

active

06934192

ABSTRACT:
An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.

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