EEPROM memory having an improved resistance to the breakdown...

Details EEPROM memory having an improved resistance to the breakdown... EEPROM memory having an improved resistance to the breakdown...

2007-05-29

2009-02-17

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185300

Reexamination Certificate

active

07492639

ABSTRACT:
The present invention relates to a method for programming or erasing memory cells that include a selection transistor connected to a floating-gate transistor. According to the method, a non-zero compensation voltage is applied to the gate of a transistor not involved in the programming or erasing process so as to increase a breakdown threshold of the transistor, and an inhibition voltage is applied to the gate or to a terminal of at least one floating-gate transistor connected to the transistor having its breakdown threshold increased to inhibit a phenomenon of soft programming or soft erase of the floating-gate transistor.

REFERENCES:
patent: 6064595 (2000-05-01), Logie et al.
patent: 6411548 (2002-06-01), Sakui et al.
patent: 6522585 (2003-02-01), Pasternak
patent: 7245534 (2007-07-01), Goda et al.
patent: 0 484 298 (1992-05-01), None
patent: 97/19452 (1997-05-01), None

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