EEPROM memory cell with a single level of polysilicon programmab

Details EEPROM memory cell with a single level of polysilicon programmab EEPROM memory cell with a single level of polysilicon programmab

1987-12-22

1990-06-19

LaRoche, Eugene R.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365185, H01L 2978, G11C 1134

Patent

active

049357905

ABSTRACT:
The cell is formed of a selection transistor, a detection transistor and a tunnel condenser. The detection Transistor has its own control gate formed with an n.sup.+ diffusion which is closed and isolated from those of the other cells of the same memory.

REFERENCES:
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patent: 4616245 (1986-09-01), Topich et al.
patent: 4630087 (1986-12-01), Momodomi
patent: 4649520 (1987-03-01), Eitan
Hsieh et al., "Electrically Alterable Memory Cell With Independent Erase Input", IBM Technical Disclosure Bulletin, vol. 23, No. 2, Jul. 1980, pp. 661-663.
"Bit-by-Bit Erasable EEPROM With Single Transitor Per Bit", Masuoka Conference: International Electron Devices Meeting, Washington, D.C., U.S.A., Dec. 7-9, 1981, IEDM 81, pp. 20-23.
"High Density Single-Poly Si Structure EEPROM with LB (Lowered Barrier Height) Oxide for VLSI's"; Matsukawa et al., 1986.
"Analysis and Modeling of Floating-Gate EEPROM Cells"; Kolodny et al.; IEEE Transaction on Electron Devices, vol. Ed-33, No. 6, Jun. 1986.
Modelling of Write/Erase and Charge Retention Characteristics of Floating Gate EEPROM Devices, A. Bhattacharyya, Solid-State Electronics, vol. 27, No. 10, pp. 899-906; 1986.
"An EEPROM for Microprocessors and Custom Logic", Cuppens et al., IEEE Journal of Solid-State Circuits, vol. SC-20, Apr. 1985.

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