EEPROM memory cell array embedded on core CMOS

Details EEPROM memory cell array embedded on core CMOS EEPROM memory cell array embedded on core CMOS

2000-06-21

2003-05-13

Tran, Michael Thanh (Department: 2818)

Static information storage and retrieval

Floating gate

C257S315000

Reexamination Certificate

active

06563731

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of electrically erasable programmable read only memory (EEPROM) devices. In particular, the present invention relates to a low cost EEPROM cell array which is embedded on core CMOS for analog applications.
BACKGROUND ART
Solid state memory is used to store digital bits (i.e., “1's and 0's) of data by means of semiconductor circuits. Solid state memory is classified as being either volatile memory or non-volatile memory. Volatile memory retains the digital bits of data only so long as power is applied and maintained to the circuits. For example, dynamic random access memory (DRAM) is often used in computer systems to temporarily store data as it is being processed by the microprocessor or CPU. Non-volatile memory, on the other hand, retains its digital bits of data, even after power has been shut off from the circuits. One common example of non-volatile memory is read-only memory (ROM). Some read-only memory can be programmed; these types of devices are known as programmable read-only memory (PROM). There exists a category of PROM devices which can be electrically erased so that they can actually be reprogrammed many times over to store different sets of data. These electrically erasable programmable read only memory are commonly referred to as EEPROMs.
EEPROM memory devices are typically comprised of an array of memory cells. Each individual memory cell can be programmed to store a single bit of data. The basic, fundamental challenge then in creating an EEPROM memory cell is to use a controllable and reproducible electrical effect which has enough nonlinearity so that the memory cell can be written or erased at one voltage in less than 1 ms and can be read at another voltage, without any change in the programmed data for more than 10 years.
Fowler-Nordheim tunneling, which was first described by Fowler and Nordheim in 1928, exhibits the required nonlinearity and has been widely used in EEPROM memories. Due to the unique physical properties of silicon (Si), the energy difference between the conduction band and the valence band is 1.1 eV. In silicon dioxide (SiO
2
), the energy difference between these bands is about 8.1 eV, with the conduction band in SiO
2
3.2 eV above that in Si. Since electron energy is about 0.025 eV at thermal room temperature, the probability that an electron in Si can gain enough thermal energy to surmount the Si-to- SiO
2
barrier and enter the conduction band in SiO
2
is very small. Thereby, if electrons are placed on a polysilicon floating gate surrounded by SiO
2
, then this band diagram will by itself insure the retention of data.
By taking advantage of this Fowler-Nordheim tunneling principle, a specific EEPROM memory cell, typically comprised of a single transistor, can be addressably programmed by applying electrical signals to a specified row and a specified column of the memory array matrix. For example, to write a logic “
1
” or a logic “
0
” into a memory cell, a voltage is applied to the control gate corresponding to the row (word line) of the selected cell, while a voltage corresponding to either a “
1
” or a “
0
” is applied to the source or drain corresponding to the column (bit line) of the selected cell. At the same time, other memory cells are prevented from being written to by applying specific voltages to their word and bit lines such that they become write inhibited. Likewise, particular memory cells can be erased while others are prevented from being erased (erase inhibited) by applying the appropriate voltages to the designated word and bit lines. By selectively applying voltages to the word and bit lines, memory cells can be read from, written to, write inhibited, erased, and erase inhibited.
As the design of EEPROM cells evolved, it has become possible to pack more and more memory cells into a single EEPROM chip. However, the increased density and efficiency of EEPROM cells has come at the expense of complexity.
FIG. 1
shows an exemplary prior art EEPROM cell. It is described in the U.S. Pat. No. 5,379,253 “High Density EEPROM Cell Array With Novel Programming Scheme And Method Of Manufacture,” issued to inventor Albert Bergemont, Jan. 3, 1995. It can be seen that this EEPROM cell design call for the use of multiple layers, including multiple polysilicon layers. Each additional layer dramatically increases the complexity for fabricating such a EEPROM cell. Although the complexity of a single memory cell has increased, scaling this memory cell design across a huge array has proven to be quite profitable because the memory needs of many applications necessitate the use of dedicated, high density EEPROM chips.
Sometimes though, EEPROM cells are used in analog applications, such as in trimming capacitors, resistors, etc. Utilizing a traditional EEPROM cell in these types of core CMOS analog applications is not cost-efficient. This is because the state-of-the-art EEPROM cell layout and structure has been optimized for stand-alone EEPROM chips. It is extremely difficult to embed these stand-alone EEPROM cells for use on core CMOS analog applications due to the complexity to fabricate them. Conventional stand alone EEPROM cell designs typically involved having a double polysilicon process with high voltage enhancement and depletion transistors. As such, they are not ideally suited for limited use in certain analog applications.
Thus, there exists a need in the prior art for a cost-effective EEPROM cell solution which can readily be embedded on core CMOS for analog applications. The present invention provides an elegant, low-cost full feature EEPROM cell array which satisfies this need.
SUMMARY OF THE INVENTION
The present invention pertains to a low-cost, novel electrically erasable programmable read only memory cell array. The EEPROM memory cell array includes a well of P− type conductivity. A first well of N-type conductivity resides within the well of P− type conductivity. A second well of N-type conductivity residing within the well of P− type conductivity spaced apart from the first well of N-type conductivity. A plurality of wells of P+ type conductivity reside within the second well of N-type conductivity. A plurality of contacts couple a plurality of bit lines to the plurality of wells of P+ type conductivity. A third well of N-type conductivity resides within the well of P− type conductivity and is spaced apart from the first well of N-type conductivity and the second well of N-type conductivity. A single polysilicon layer disposed over the first well, the second well, and the third well. This single polysilicon layer defines floating gates for a plurality of electrically erasable programmable read only memory cells of the array.
In one embodiment, the array is comprised of four EEPROM memory cells. The first memory cell is formed from a first portion of the first N-well which acts as a coupling region to the first memory cell. A first portion of the second N-well acts as a window region to the first memory cell. Two contacts are used to couple a first and second bit line to a first P+ well residing within the second N-well. A first floating gate disposed over the first and second N-wells. A first tunneling window tunnels holes to and from the first floating gate of the first memory cell. The second memory cell uses a second portion of the first N-well to act as a coupling region. A second portion of the second N-well acts as a window region to the second memory cell. Two contacts couple a third and a fourth bit line to the P+ well. A second floating gate is disposed over the first and second N-wells. The second memory cell has its own tunneling window which tunnels holes to and from the second floating gate. The third memory cell is comprised of a first portion of the third N-well which acts as a coupling region. A third portion of the second N-well acts as a window region to the third memory cell. Two contacts are used to couple the first and second bit lines to a third P+ well residing also within the s

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