Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-01-12
2001-04-24
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C257S243000
Reexamination Certificate
active
06222766
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an EEPROM (electrically erasable and programmable ROM) memory cell and a method of fabricating the same, and more particularly, it relates to a novel EEPROM memory cell.
A conventional mass storage flash EEPROM memory
1
generally has a cell structure of a stacked MOSFET (hereinafter referred to as the CGFET) using gates
2
and
3
of two polysilicon (polycrystal silicon) layers as shown in
FIG. 10. A
charge storage portion in this structure corresponds to the floating gate
2
, and electrons are injected/drawn through a tunnel oxide film
4
in general. Since this structure includes the gates
2
and
3
of two polysilicon layers, the fabrication process is complicated. In addition, owing to the complicated fabrication process, reliability is difficult to secure.
On the other hand, a typical example of a device including a gate of one polysilicon layer is an MNOS memory cell
5
as shown in FIG.
11
. The MNOS memory cell
5
includes two gates
6
and
7
of polysilicon, and a silicon nitride (Si
3
N
4
) layer
8
and a thin thermally oxidized silicon film
9
are used as a gate insulating film. Data are written or erased in this memory cell while charge is stored in a trap formed in the vicinity of the interface between the silicon nitride layer
8
and the thermally oxidized silicon film
9
by the tunnel effect. Since this memory cell includes the two gates
6
and
7
aligned on the same plane, the area thereof is so large that higher integration is difficult to attain.
The applicant of the present invention searched for related arts before filing the present application, and found out an invention concerning an improved MNOS memory cell of this type, which is disclosed in National Publication of translated version No. 8-506693 (PCT/US93/05669). The invention disclosed in this publication relates to a flash EEPROM cell
130
including a single polysilicon layer as shown in FIGS.
12
(
a
) and
12
(
b
), and this cell
130
includes a (access) transistor
158
and an EEPROM transistor
162
. The EEPROM transistor
162
includes a floating gate
160
and a control gate
142
, so that charge can be stored in the floating gate
160
in the same manner as in the aforementioned conventional memory cell. In this flash EEPROM cell
130
, the access transistor
158
, the EEPROM transistor
162
and the control gate
142
forming a capacitor
170
are disposed on the same plane. Accordingly, the flash EEPROM cell
130
occupies a larger integration area than the conventional EEPROM memory cell, which is disadvantageous in attaining a high packing density.
This flash EEPROM cell
130
has the structure including the (access) transistor
158
and the EEPROM transistor
162
. Furthermore, the flash EEPROM cell
130
includes the floating gate
160
and the control gate
142
, and charge is stored in the floating gate
160
.
Thus, there is a need for a memory cell with a gate structure including a single polysilicon layer so as to simplify the fabrication process, improve the productivity and lower the fabrication cost of the memory cell.
There is also a need for a memory cell with a simple structure as well as to reduce the area of the memory cell so as to attain high integration.
There is also a need for processes to form a fine memory cell by utilizing DHE (drain channel hot electrons) and GIDL (gate induced drain leakage).
SUMMARY OF THE INVENTION
The invention provides an EEPROM memory cell has a structure including only one polysilicon layer. The invention also enables the fabrication process can be simplified, the productivity to be improved, and the fabrication cost to be lowered. The EEPROM memory cell of the present invention has a simple structure and includes only one gate in a plane, making it advantageous in forming a fine memory cell. Thus, the invention permits reduction in area of the memory cell and enables high integration to be realized.
In one aspect, the invention encompasses an EEPROM memory having a MOSFET structure comprising a source region and a drain region formed on a surface of a substrate; a channel region defined on the surface of the substrate between the source region and the drain region; and a gate oxide film and a gate formed on the channel region, so that it is operated as a memory. A charge storage portion of this EEPROM memory cell is preferably a tunnel oxide film formed in the vicinity of the drain region, and the drain region and the gate oxide film (and the gate thereon) are preferably formed to have a large overlap region therebetween so as to easily generate a GIDL. In this EEPROM memory cell, data may be written by trapping hot electrons in the gate oxide film, and data is erased by injecting holes into the gate oxide film. Also, data may be read from this EEPROM memory cell by observing change of the GIDL in the drain region under application of a negative voltage to the gate.
The invention also encompasses methods of making EEPROM memory cells.
These and other aspects of the invention are described in further detail below.
REFERENCES:
patent: 5606521 (1997-02-01), Kuo et al.
Sasaki Katsuto
Tsujimura Tsutomu
Capella Steven
Fears Terrell W.
International Business Machiness Corporation
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