EEPROM memory cell and driving circuitry

Details EEPROM memory cell and driving circuitry EEPROM memory cell and driving circuitry

1987-06-18

1989-02-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 43, 357 235, 365185, H01L 21265, H01L 2170

Patent

active

048046370

ABSTRACT:
An electrically erasable programmable memory device which includes a floating gate, heavily doped source and drain regions in which one side thereof is laterally spaced from the floating gate, and the other side has a lightly doped "reach-through" region between the heavily doped region and the channel that underlies the floating gate. A control gate overlies the floating gate. The oxide thickness between the gate and channel is sufficiently thin such that electron tunnleing takes place between the floating gate and the "reach through" region.

REFERENCES:
patent: 4004159 (1977-01-01), Rai et al.
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 4566175 (1986-01-01), Smayling et al.
patent: 4573144 (1986-02-01), Countryman, Jr.
patent: 4590665 (1986-05-01), Owens et al.

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