Static information storage and retrieval – Floating gate – Particular biasing
Patent
1989-12-18
1991-09-24
Gossage, Glenn
Static information storage and retrieval
Floating gate
Particular biasing
36518909, 365218, 36523006, G11C 1606
Patent
active
050519530
ABSTRACT:
An electrically erasable nonvolatile semiconductor device of a high density of integration includes a memory matrix array formed of a plurality of MOS memory transistors. In an erasing operation, a voltage to turn off one selected MOS memory transistor is applied to the control gate electrode of the selected MOS memory transistor. At the same time, a voltage near the breakdown voltage of the selected MOS memory transistor is applied to the first electrode (e.g.--source electrode) of the selected MOS memory transistor and a predetermined voltage is applied to the second electrode (e.g.--drain electrode) of the same MOS memory transistor.
REFERENCES:
patent: 4387447 (1983-06-01), Klaas et al.
patent: 4425632 (1984-01-01), Iwahashi et al.
patent: 4437172 (1984-03-01), Masuoka
patent: 4437174 (1984-03-01), Masuoka
patent: 4698787 (1987-10-01), Mukherjee et al.
Physics of Semiconductor Devices, Second Edition; S. M. Sze; Bell Laboratories, Incorporated; Murray Hill, New Jersey; pp. 88 and 99.
1987 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, "Nonvolatile Memory"; pp. 76, 77 and 345; Samachisa et al, Feb. 25, 1987.
Kitazawa Shooji
Ono Takashi
Gossage Glenn
OKI Electric Industry Co., Ltd.
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