Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1998-08-20
2001-02-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030, C365S185250, C365S185240, C365S185110
Reexamination Certificate
active
06195285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a type of semiconductor memory called an EEPROM (electrically erasable programmable read-only memory) device that allows rewriting of data to be performed individually in each memory cell.
2. Description of the Prior Art
An EEPROM device includes a number of memory cells each composed of, as shown in
FIG. 7
, a MOS-type FET (hereafter referred to as the “memory transistor”) MT having a floating gate (a gate that is insulated from the surroundings) between a control gate CG and a conducting channel formed between a drain D
M
and a source S
M
within a silicon substrate, and a MOS-type FET (hereafter referred to as the “selection transistor”) ST. To achieve storage of data, an EEPROM device exploits the fact that the threshold voltage of the memory transistor MT with respect to the control gate CG varies with the amount of electric charge accumulated in the floating gate FG. Note that part of the insulator (oxide film) between the floating gate FG and the drain D
M
is made thinner than its remaining part so that, by way of this thin part, electrons are injected into and expelled out of the floating gate FG by the tunnel effect.
The amount of electric charge accumulated in the floating gate FG of the memory transistor MT is usually so controlled that, as shown in
FIG. 8
, the threshold voltage of the memory transistor MT falls within one of two ranges that correspond to values “0” and “1” respectively. In this way, one bit of data is stored in each memory cell.
Note that, to read data from a memory cell of a one-bit-per-cell type as described above, it is necessary to prepare, as a voltage to be applied to the control gate CG of the memory transistor MT, a reference voltage E (see
FIG. 8
) that is approximately intermediate between the above-mentioned two ranges of the threshold voltage.
In recent years, to cope with demand for larger storage capacity, much research has been done in the field of so-called multivalued storage that aims to store two or more bits of data in one memory cell. For example, by controlling the amount of electric charge accumulated in the floating gate FG of the memory transistor MT in such a way that, as shown in
FIG. 9
, the threshold voltage of the memory transistor MT falls within one of four ranges that correspond to values “00”, “01”, “10”, and “11” respectively, it is possible to store two bits of data in one memory cell.
Note that, to read data from a memory cell of a two-bits-per-cell type as described above, it is necessary to prepare, as voltages to be applied to the control gate CG of the memory transistor MT, a first reference voltage E
1
, a second reference voltage E
2
, and a third reference voltage E
3
(see
FIG. 9
) that are approximately intermediate between the above-mentioned four ranges of the threshold voltage.
In an EEPROM device, writing of data to a memory cell is performed in the following manner. First, a high-level voltage (for example, 15 V) is applied to the gate G and the drain D
S
of the selection transistor ST, with the control gate CG of the memory transistor MT grounded and with the source S
M
of the memory transistor MT kept open (i.e. non-connected). This causes electrons to be expelled out of the floating gate FG of the memory transistor MT.
To control the amount of electric charge accumulated in the floating gate FG in accordance with the data to be written in, whereas the high-level voltage applied to the gate G and the drain D
S
of the selection transistor ST is kept constant regardless of the data to be written in, the duration of data writing is varied in accordance with the data to be written in.
Specifically, the longer the data writing duration, the greater the number of electrons expelled out of the floating gate FG and therefore the more the threshold voltage of the memory transistor MT drops. In contrast, the shorter the data writing duration, the smaller the number of electrons expelled out of the floating gate FG and therefore the less the threshold voltage drops.
Note that, before writing of data, erasing is performed. This causes a predetermined amount of electric charge to be accumulated in the floating gate FG and thereby makes rewriting of data possible.
As described above, in a conventional EEPROM device, the duration of data writing is controlled in accordance with the data to be written in. However, a process that depends on control of duration tends to cause unduly large variations in the distribution of the threshold voltage of the memory transistor MT, leading in some cases to garbled data. Moreover, controlling the duration of data writing naturally results in longer writing times with particular types of data than with other types of data, and thus, on the whole, requires longer writing times.
These inconveniences of a conventional EEPROM device are becoming increasingly intolerable as multivalued storage technology advances, that is, as more and more bits of data are stored in one memory cell.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an EEPROM device that can perform writing of data with higher accuracy and with reduced time on the whole.
To achieve the above object, according to the present invention, an EEPROM device that has a memory transistor having a floating gate between a control gate and a conducting channel formed between a drain and a source and that achieves storage of data by exploiting the fact that the threshold voltage of the memory transistor varies with the amount of electric charge accumulated in the floating gate is so designed that, during writing of data, the voltage between the drain and the control gate of the memory transistor is varied in accordance with the data to be written in.
Here, after the completion of erasing, if the duration of data writing is kept constant, then the amount of electric charge accumulated in the floating gate FG of the memory transistor MT depends on the voltage between the drain D
M
and the source S
M
of the memory transistor MT and on the voltage between the drain D
M
and the control gate CG of the same transistor.
Based on this principle, in this structure, even if the data writing duration is kept constant, it is still possible to control the amount of electric charge accumulated in the floating gate FG of the memory transistor MT in accordance with the data to be stored. That is, it is possible, during writing of data, to keep the data writing duration constant regardless of the data that is going to be written in.
REFERENCES:
patent: 5615149 (1997-03-01), Kobayashi et al.
patent: 5708600 (1998-01-01), Hakozaki et al.
patent: 5748530 (1998-05-01), Gotou et al.
patent: 5870218 (1999-02-01), Jyouno et al.
patent: 5892714 (1999-04-01), Choi
patent: 5912842 (1999-06-01), Chang et al.
patent: 5970012 (1999-10-01), Takeshima
Tada Yoshihiro
Yamamoto Hiroki
Arent Fox Kintner Plotkin & Kahn
Nelms David
Rohm & Co., Ltd.
Yoha Connie C.
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