Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-28
2003-04-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185050, C365S185080, C365S185090
Reexamination Certificate
active
06556480
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Application
The present invention is directed toward an EEPROM circuit, in particular a microcontroller that includes an EEPROM for storing program code and data that is capable of being written to and read from simultaneously. More specifically, the present invention relates to an EEPROM circuit comprising:
a program array of a matrix of EEPROM cells arranged in columns and rows,
a data array of a matrix of EEPROM cells arranged in columns and rows, said cells of said program and data array capable of being written, read, and erased;
a reference voltage circuit coupled to said program array capable of producing voltages used to write to and erase data from said program array; and
a current generation circuit coupled to said program array for supplying current to said array in operation.
2. Description of the Related Art
Many microcontrollers require embedded non-volatile memory blocks to store the system code, or programs that the microcontrollers execute. For some applications, a ROM memory can be used to store this system code, but this prohibits later changes from being made to the code. If the system code needs to be changed, a flash PROM is sometimes used.
Additionally, many microcontrollers store data from computation results. In this case, use of an EEPROM is preferred, rather than the flash PROM used above, because of the ability to selectively delete some of the data stored That is, using an EEPROM, it is possible to delete only a portion of the previously stored data while leaving the desired data untouched. Flash PROMs do not have this sectional erase capability.
If a particular microcontroller requires an EEPROM for a data storage section, then the non-volatile memory that stores the system code must also be an EEPROM, because it is prohibitively expensive and inconvenient to produce both an EEPROM and a Flash PROM on a single substrate for the microcontroller. It is expensive to produce such a chip because the processes that make EEPROMs and Flash PROMs are vastly different and incompatible with one another. Therefore, in those microcontrollers that store both programs and data, because the data storage cells must be EEPROMs, the program storage cells must also be EEPROMs.
Microcontrollers that have two EEPROM sections normally have two complete and separate EEPROM macrocells. An EEPROM macrocell is a preformatted layout scheme that includes all of the necessary circuit sections for proper EEPROM operation. It includes a set of HV latches in which data to be programmed are temporarily latched prior to programming them into the EEPROM cells. It also includes a charge pump for generating the high voltages necessary to program and erase the EEPROM cells.
It would be impossible to use a single EEPROM section to store both the system code and stored data from the computation results because of different functionality needed for these two processes. The system code portion needs to be executed (read) at the same time that data is being written (programmed). In conventional systems, this is impossible, because one task would have to wait for the other. It takes about 4/5 ms to program data into an EEPROM, during which time the system code could not be read. That time period is an impossibly long time period to have the microprocessor sit idle because no further portions of the system code could be read while data was being written. If the microprocessor was forced to be idle for this time period, it could not service interrupts during the entire 4/5 ms time period. Many systems specify that interrupts must be serviced much faster than 4/5 ms, thus the system code and data must be stored separately so that they can be accessed separately.
Requiring two separate EEPROM macrocell blocks causes inefficiency, however. As noted above, most current designs use pre-made macroblocks to reduce design cost. That is, instead of creating a complete EEPROM portion from nothing, a standard cell library is used. In the case where two EEPROM portions are used, such as where both the system code and the data need to be in EEPROM blocks, using two standard macrocells causes many inefficiencies. One inefficiency is that typically the data EEPROM is much smaller than the EEPROM used to store the system code. Thus, using two identical preformatted macroblocks results in one EEPROM being underutilized. For example, a standard EEPROM macrocell may be 8 k in size, with 32 columns. That would mean there are 256 rows in that standard macrocell. It would be fairly easy to change this standard macrocell to be smaller, such as to 128 bytes, by simply removing the unnecessary rows. However, in that case, the charge pump and HV latches would be much larger than they would necessarily have to be, because they were originally designed to handle 32 columns and 256 rows, but are now only being used for 4 rows. The data storing EEPROM macrocell can be redesigned and optimized for efficiency to its size, for instance, by reducing the size of the charge pump and reducing the number of columns, but redesigning the smaller EEPROM results in an inefficiency that was hoped to be avoided by using the macrocell in the first place.
The technical problem addressed by this invention is to provide an EEPROM that can have data written to a data memory array at the same time that data is read from a program memory array.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides a single macrocell that can perform Read While Write (RWW) functions. Data and program (system code) memory space is provided in a single macrocell designed to eliminate redundant components.
The macrocell includes two memory arrays, one for storing data, and one for storing the system code, or program. A charge pump for high voltage generation and high voltage latches remain similar to that of a single macrocell, but are shared across both the program and data memory arrays.
Presented is an EEPROM circuit of the type described above and comprising:
a program array of a matrix of EEPROM cells arranged in columns and rows;
a data array of a matrix of EEPROM cells arranged in columns and rows, said cells of said program and data array capable of being written to, read from, and erased;
a reference voltage circuit coupled to said program array capable of producing voltages used to write to and erase data from said program array;
a current generation circuit coupled to said program array for supplying current to said program array in operation; wherein said reference voltage circuit and said current generation circuit are additionally coupled to said data array; and
means for selectively connecting at least one of the rows of said program array to one of the rows of said data array, and for selectively connecting at least one of the columns of said program array to one of the columns of said data array.
Also presented is a method of operating an EEPROM circuit of the type described above, the EEPROM circuit comprising:
a program array of a matrix of EEPROM cells arranged in columns and rows,
a data array of a matrix of EEPROM cells arranged in columns and rows, said cells of said program and data array capable of being written, read, and erased;
a reference voltage circuit coupled to said program and data arrays capable of producing voltages used to write to and erase data from said arrays;
a current generation circuit coupled to said program and data arrays for supplying current to said arrays in operation, the method comprising:
accepting signals to the EEPROM circuit for writing data to said program array and writing data to said program array;
accepting signals to the EEPROM circuit for writing data to said data array and writing data to said data array;
accepting signals to the EEPROM circuit for reading data from said program array and reading data to said program array;
accepting signals to the EEPROM circuit for reading data from said data array and writing data to said data array; and
accepting signals to the EEPROM circuit for reading data from said program array while writin
Iannucci Robert
Jorgenson Lisa K.
Nelms David
Pham Ly Duy
Seed IP Law Group PLLC
LandOfFree
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