EEPROM cells and array with reduced write disturbance

Details EEPROM cells and array with reduced write disturbance EEPROM cells and array with reduced write disturbance

2001-12-20

2003-11-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S230030

Reexamination Certificate

active

06643174

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
NOT APPLICABLE
STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
NOT APPLICABLE
REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAM LISTING APPENDIX SUBMITTED ON A COMPACT DISK.
NOT APPLICABLE
BACKGROUND OF THE INVENTION
The present invention relates to flash electrically-erasable, programmable read-only memories (EEPROMs). In particular, the present invention relates to flash EEPROMs having selectable source connections.
U.S. Pat. No. 5,812,452 (which is incorporated herein by reference in its entirety for all purposes) describes a block accessible flash EEPROM. Each memory cell includes two transistors: a select transistor and a storage transistor. The select transistor is connected in series with the storage transistor. When placed in a memory array, a predefined number of memory cells can be grouped into blocks. By using a block select transistor, the memory cells can be accessed and altered on a block-by-block basis.
One issue is not disclosed in U.S. Pat. No. 5,812,452. During a programming (write) operation on selected memory cells, the unselected memory cells that share the same source connection with the selected memory cells will be exposed to a high voltage stress of approximately 12 volts. This high voltage stress may eventually degrade these unselected cells, possibly causing these cells to alter their storage states (i.e., to fail) depending upon the level of stress and its duration. Such a condition is termed write disturbance.
There is a need for a flash EEPROM architecture that does not expose unselected memory cells to high voltage stress.
BRIEF SUMMARY OF THE INVENTION
According to one embodiment, a flash EEPROM includes a plurality of groups of memory cells, one or more source lines, and a plurality of source select transistors. The source lines are coupled to selectively provide a source voltage. The source select transistors are configured to selectively couple the source lines to selected groups of memory cells. In a programming operation, selected source lines are charged to the source voltage. Selected source select transistors then couple the selected source lines to the selected groups of memory cells. In this manner, only the selected groups of memory cells are exposed to the source voltage. For the groups of memory cells that are not selected, their source select transistors do not couple them to their source lines, so the unselected groups of memory cells are not exposed to the source voltage.


REFERENCES:
patent: 5452251 (1995-09-01), Akaogi et al.
patent: 5592415 (1997-01-01), Kato et al.
patent: 5812452 (1998-09-01), Hoang

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