Static information storage and retrieval – Floating gate – Particular biasing
Patent
1994-04-11
1995-11-28
Nelms, David C.
Static information storage and retrieval
Floating gate
Particular biasing
365182, 365218, 257314, 257315, G11C 1134, H01L 2968
Patent
active
054714222
ABSTRACT:
An EEPROM cell (40) includes a floating gate transistor (47) and an isolation transistor (45). Both a floating gate (48) and an isolation gate (46) are formed on a tunnel dielectric (44) within the cell. The isolation gate is coupled to a doped source region (52) of the floating gate transistor. The isolation transistor is not biased during a program operation of the cell, enabling a thin tunnel dielectric (less than 120 angstroms) to be used beneath all portions of both gates within the cell. Thus, the need for both a conventional tunnel dielectric and a gate dielectric is eliminated. The cell tolerates over-erasure, can be programmed at low programming voltages, and has good current drive due to the thin tunnel dielectric throughout the cell.
REFERENCES:
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4420871 (1983-12-01), Scheibe
patent: 4816883 (1989-03-01), Baldi
patent: 4907197 (1990-03-01), Uchida
patent: 5021848 (1991-06-01), Chiu
patent: 5049516 (1991-09-01), Arima
patent: 5081054 (1992-01-01), Wu et al.
patent: 5216268 (1993-06-01), Chen et al.
Chang Ko-Min
Chang Kuo-Tung
Shum Danny P.
Goddard Patricia S.
Hoang Huan
Motorola Inc.
Nelms David C.
LandOfFree
EEPROM cell with isolation transistor and methods for making and does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with EEPROM cell with isolation transistor and methods for making and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and EEPROM cell with isolation transistor and methods for making and will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2018251