EEPROM cell with integral select transistor

Details EEPROM cell with integral select transistor EEPROM cell with integral select transistor

1988-05-09

1989-03-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 30, 437 43, 437 44, H01L 2994, H01L 2978

Patent

active

048142867

ABSTRACT:
An electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the folating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.

REFERENCES:
patent: 4114255 (1978-09-01), Sodbery
patent: 4203158 (1980-05-01), Mar et al.
patent: 4258378 (1981-03-01), Wall
patent: 4266283 (1981-05-01), Perlegos et al.
patent: 4328565 (1982-05-01), Harari
patent: 4364075 (1982-12-01), Bohr et al.
patent: 4412311 (1983-10-01), Miccoli et al.
patent: 4566175 (1986-01-01), Smayling et al.
patent: 4590503 (1986-05-01), Harari et al.
patent: 4622656 (1986-11-01), Kamiya et al.
patent: 4646425 (1987-03-01), Owens et al.
patent: 4757026 (1988-07-01), Woo et al.

Affiliated with

Also associated with

Rating

EEPROM cell with integral select transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with EEPROM cell with integral select transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and EEPROM cell with integral select transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-476859