Static information storage and retrieval – Floating gate
Reexamination Certificate
2000-07-21
2001-05-29
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
C257S401000, C257S315000, C257S316000
Reexamination Certificate
active
06240011
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an EEPROM cell with improved current performance and to the relative building process.
BACKGROUND OF THE INVENTION
The demand for larger EEPROM memories imposes greater efforts in smaller dimensions for memory cells. If the area of an elementary cell is decreased, and in particular if the dimension of the active area is decreased, there are risks of decreasing the value of the current that flows in the cell during the reading phase. In EEPROM cells the value of the driving current is determined in part by the selection transistor of the bit line that is set in series to the cell itself.
The selection transistor has different design characteristics that are partially contrasting. Particularly, it must have a threshold voltage sufficiently high in order to stop the current when its corresponding cell is not selected, and it must bear a higher current than that of the single cell when it is in a reading phase. In order to be able to bear the driving current of the cell, the active area of the selection transistor has greater dimensions than the dimensions of the active area of the memory cell.
The source of the selection transistor is directly connected to the drain of the floating gate memory cell, preferably it is only one active area. This active area, in the zone of passage from the source area and the drain area, presents two pair of edges, that as a whole, as seen in a top plan view, have a shape substantially similar to that of a funnel just in the zone where the capacitor implants are formed and where the tunnel oxide is grown. This is a very critical zone and during the growth of the oxide crystallographic defects could occur that can create structural stress.
SUMMARY OF THE INVENTION
The disclosed embodiment of the present invention is directed to an EEPROM cell, comprising a memory cell and a selection transistor, and having smaller dimensions according to the manufacturing process while avoiding limitations of the maximum bearable current and overcoming problems of the known art relatively to the defects associated with the edges. According to the embodiments of the present invention, the foregoing is attained by means of an EEPROM cell comprising a selection transistor having a drain region, a source region and a control gate, a memory cell having a drain region, a source region, a control gate and a floating gate, said drain region of said memory cell and said source region of said selection transistor are connected together, and the source and drain regions of said memory cell and the source and drain regions of said selection transistor have an area of value respectively increasing.
The foregoing is attained by means of a process for the building of an EEPROM cell comprising forming a floating gate memory cell having an active area, forming a selection transistor of said memory cell on a substrate having an active area, and by forming said active areas of said memory cell and of said selection transistor respectively of linearly increasing dimension.
REFERENCES:
patent: 5410171 (1995-04-01), Tsuzuki et al.
patent: 5424569 (1995-06-01), Prall
patent: 5973360 (1999-10-01), Tihanyi
Dalla Libera Giovanna
Patelmo Matteo
Galanthay Theodore E.
Le Vu A.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
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