EEPROM cell using P-well for tunneling across a channel

Details EEPROM cell using P-well for tunneling across a channel EEPROM cell using P-well for tunneling across a channel

1998-12-21

1999-10-19

Phan, Trong

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518521, 36518526, 36518529, 365218, G11C 1604

Patent

active

059699922

ABSTRACT:
An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a P-well of a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.

REFERENCES:
patent: 4715014 (1987-12-01), Tuvell et al.
patent: 4924278 (1990-05-01), Logie
patent: 5742542 (1998-04-01), Lin et al.
patent: 5761116 (1998-06-01), Li et al.

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