EEPROM cell structure and architecture with increased capacitanc

Details EEPROM cell structure and architecture with increased capacitanc EEPROM cell structure and architecture with increased capacitanc

1992-02-10

1994-04-12

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 257314, G11C 1300

Patent

active

053031857

ABSTRACT:
AN EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

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R. Kazerounian et al., A 5 Volt High Density Poly-Poly Erase Flash EPROM Cell, IEDM-88 (Dec. 11).
J. Miyamoto, et al., A 1.0 .mu.m CMOS/Bipolar Technology for VLSI Circuits. IEDM-83, (see FIG. 2).
T. Mizuno et al., Si.sub.3 N.sub.4 /SO.sub.2 Spacer Induced High Reliability in LDDMOSFET and Its Simple Degradation Model, IEDM-88 (see FIG. 1).
An Asymmetrical Lightly-Doped Source (Alds) Cell for Virtual Ground High Density EPROM. K. Yoshikawa et al., IEDM-88.

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