EEPROM cell having a floating-gate transistor within a cell...

Details EEPROM cell having a floating-gate transistor within a cell... EEPROM cell having a floating-gate transistor within a cell...

2005-01-11

2005-01-11

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185140, C365S185020, C257S315000, C257S316000

Reexamination Certificate

active

06842372

ABSTRACT:
An EEPROM memory device includes a substrate of a first conductivity type having a cell well region of a second conductivity type therein. A floating-gate transistor of the first conductivity type resides in the cell well region and includes a first region separated from a second region by a channel region. A write transistor of the second conductivity type resides in the substrate and includes a first region separated from a second region by a channel region. The second region partially extends into the cell well region and forms a p-n junction with the second region of the floating-gate transistor. The process for fabricating the EEPROM device includes forming the cell well region in the substrate by creating a retrograde doping profile. In operation, the EEPROM device transfers electrons between the cell well region and the floating-gate electrode during both programming and erasing operations.

REFERENCES:
patent: 6028789 (2000-02-01), Mehta et al.
patent: 6064595 (2000-05-01), Logie et al.
patent: 6208559 (2001-03-01), Tu et al.
patent: 6215700 (2001-04-01), Fong et al.
patent: 6282123 (2001-08-01), Mehta
patent: 20010022359 (2001-09-01), Mehta

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