EEPROM cell array with tight erase distribution

Details EEPROM cell array with tight erase distribution EEPROM cell array with tight erase distribution

1993-06-29

1994-10-11

Thomas, Tom

Fishing, trapping, and vermin destroying

437 43, 437 48, H01L 2170

Patent

active

053547039

ABSTRACT:
An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11). The program and erase regions of each cell are physically separate from each other, and the characteristics of each of those regions may be made optimum independently from each other. Field oxide insulators (25) defining the channels (Ch) and the source line (17) have straight-line edges adjacent the source line (17) and adjacent the channel (Ch).

REFERENCES:
patent: 4426764 (1984-01-01), Kosa et al.
patent: 5019527 (1991-05-01), Ohshima et al.

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