EEPROM cell

Static information storage and retrieval – Floating gate – Particular biasing

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365189, G11C 1140

Patent

active

048036625

ABSTRACT:
An EEPROM cell for a memory device comprises a pair of bit lines each including a floating-gate MOS transistor such that a selected one of the transistors can be charged while the other is in uncharged condition by applying a higher voltage to a corresponding one of the bit lines and a lower voltage to the other bit line. Information stored in such a cell can thus be rewritten simply by applying a high voltage to one of the pair of its bit lines without carrying out a time-consuming ERASE mode of operation.

REFERENCES:
patent: 4467451 (1984-08-01), Moyer

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