Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-01-18
2003-09-02
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185180, C365S185280
Reexamination Certificate
active
06614692
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to electrically erasable, programmable read only memory (EEPROM) arrays and methods for operation thereof, and more particularly, to nitride read only memory (NROM) EEPROM arrays and inhibiting disturbs in such arrays.
BACKGROUND OF THE INVENTION
EEPROM arrays are utilized for storage of data Typically, the data stored therein can be changed, either by programming or erasing, multiple times over the lifetime of the array. As in all non-volatile memory arrays, each cell is individually programmed; however, in contrast to either erasable, programmable read only memory (EPROM) or FLASH arrays, in EEPROM arrays each cell can also be individually erased.
Typical memory uses a single bit per cell, wherein electrical charge is stored on the floating gate of each cell. Within each cell, two possible voltage levels exist. The levels are controlled by the amount of charge that is stored on the floating gate; if the amount of charge on the floating gate is above a certain reference level, the cell is considered to be in a different level. Accordingly, each cell is characterized by a specific threshold voltage (V
t
. Programing the cell increases threshold voltage V
t
, whereas erasing the cell decreases threshold voltage V
t
.
Non-volatile memory arrays comprise rows and columns of memory cells connected to word lines (rows of the array) and bit lines (columns). Each memory cell is connected to one word line and at least one bit line. Another terminal of the memory cell is connected either to another bit line (in which case, one of the bit lines is called the drain line and the other is the source line), or to a common line, such as a common source ground, depending on the array architecture. Programing or erasing an individual cell requires application of certain voltages to the word line and bit lines.
Generally when programming or erasing a cell, one or more of the neighboring cells may also be affected by the programming/erasing operation, causing thereto a possible change in their threshold voltage. This unwanted change in threshold voltage of unselected cells is known in the art as the disturb problem, herein a “disturb”. A similar effect also occurs during a read operation. However, due to the relative weakness of the applied voltage levels, the effect is significantly smaller.
A standard prior art solution to the disturb problem in EEPROM arrays is to use two transistors per memory bit of the array, i.e., in addition to the memory transistor, a select transistor is also incorporated per cell. The select transistor usually disconnects the drain of the unselected memory transistors from the drain voltages used in the programming/erasing operations. The use of a select transistor per cell, however, significantly increases the area of the memory array.
SUMMARY OF THE INVENTION
The present invention seeks to solve the abovementioned disturb problem. In the present invention, an unselected memory cell that can experience a possible drop in threshold voltage is inhibited from being erased by application of an inhibit word line voltage to the gate of the unselected cell. The term “inhibiting” as used throughout the specification and claims refers to reducing, minimizing or even eliminating the disturb effect.
The magnitude of the gate voltage is selected such that the difference between the drain or source and gate voltages applied to the unselected cell is sufficiently small so that the threshold voltage of the unselected cell does not drop below a predetermined value. By application of the inhibit voltage, it is possible to achieve negligible erasure of the unselected cell, even during relatively long erasure times and multitudes of selected cell accesses.
In a virtual ground array, the application of a relatively high voltage to the word line of a selected cell being programmed may cause a voltage propagation along unselected bit lines, thereby tuning on the cells along the unselected bit lines. In accordance with a preferred embodiment of the present invention, the voltage propagation is blocked by isolation zones positioned alongside bit lines. The isolation zones may be positioned so as to isolate a single column of memory cells or a slice of a plurality of columns.
In accordance with a preferred embodiment of the present invention the EEPROM array comprises nitride read only memory (NROM) cells. Each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells, by using inhibit voltages as described hereinbelow.
There is thus provided in accordance with a preferred embodiment of the present invention, a method for operating an electrically erasable programmable read only memory (EEPROM) array, the method including providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, one of the bit lines serving as a source and the other bit line serving as a drain, selecting one of the memory cells, and erasing a bit of the selected memory cell, while applying an inhibit word line voltage to a gate of an unselected memory cell.
In accordance with a preferred embodiment of the present invention the memory cells are non-floating gate memory cells.
Further in accordance with a preferred embodiment of the present invention the memory cells are nitride read only memory (NROM) cells. The NROM cells may be single bit, or alternatively, they may have more than one bit.
Still further in accordance with a preferred embodiment of the present invention the array is a virtual ground array.
The unselected memory cell may or may not share the same bit line as the selected cell, In accordance with a preferred embodiment of the present invention the inhibit gate voltage is of such magnitude that a threshold voltage of the unselected memory cell is lowered not more than a predetermined amount.
Further in accordance with a preferred embodiment of the present invention the erasing includes applying to the selected memory cell a negative gate voltage, a positive drain voltage and a floating source voltage.
Still further, in accordance with a preferred embodiment of the present invention, at least one column of the memory cells is placed between a pair of isolation zones, the isolation zones defining therebetween a slice of word lines and bit lines.
There is also provided in accordance with a preferred embodiment of the present invention a method for operating an EEPROM array, the method including providing an array including a multiplicity of NROM cells, wherein each memory cell is connected to a word line and to two bit lines, one of the bit lines serving as a source and the other bit line serving as a drain, selecting one of the memory cells, and performing an operation on a bit of the selected memory cell, the operation including at least one of programming and erasing, while applying an inhibit word line voltage to a gate of an unselected memory cell.
There is also provided in accordance with a preferred embodiment of the present invention an EEPROM array, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells. In contrast to the prior art, there is no need for a select transistor for each bit or cell.
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Bloom Ilan
Eitan Boaz
Eliyahu Ron
Maayan Eduardo
Eitan, Pearl, Latzer & Cohen-Zedek, LLP.
Ho Hoai V.
Saifun Semiconductors Ltd.
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