EEPROM architecture and programming protocol

Details EEPROM architecture and programming protocol EEPROM architecture and programming protocol

2005-02-22

2005-02-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185230, C365S185250

Reexamination Certificate

active

06859391

ABSTRACT:
An EEPROM memory circuit in which the loading of the column latches can be performed simultaneously with reading of the memory array. In this memory circuit, the data input connects directly to the column latches, leaving the bit lines open for memory reading by the sense amplifiers, which is connected directly to the bit lines. Two separate Y address decoders, one feeding into the column latches and the other into the bit line select circuit, provide column latch and bit line selection respectively.

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