EEPROM and method of driving the same

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518511, 36518518, 365218, G11C 1602

Patent

active

059634782

ABSTRACT:
An EEPROM includes a multiplicity of memory cells which are disposed in a memory cell array and can be addressed through the use of word, bit and source lines for writing, reading out and erasing. The memory cells which can be addressed through a single word line are divided into a multiplicity of groups, of which each is assigned a separate common source line. A method of driving the EEPROM carries out a group-by-group writing to, reading from and/or erasing of the memory cells which can be addressed through a single word line.

REFERENCES:
patent: 5033023 (1991-07-01), Hsia et al.
patent: 5065364 (1991-11-01), Atwood et al.
patent: 5745417 (1998-04-01), Kobayashi et al.

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