Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-02-12
2001-04-03
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230, C365S185260
Reexamination Certificate
active
06212102
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to an EEPROM formed of a plurality of memory cells, which are programmable, readable and erasable via selection, control, bit and source lines. Each of the memory cells contains a memory transistor and a selection transistor connected in series with the memory transistor. A drain terminal of the memory transistor is connected to the bit line and the source terminal of the selection transistor is connected to the source line.
EEPROMs are nonvolatile, electrically programmable and electrically erasable memories. The nucleus of each memory cell of an EEPROM is its memory transistor.
The memory transistor, like “normal” transistors, that is, transistors without a memory, has a source segment embedded in a substrate, a drain segment also embedded in the substrate, and a (control) gate segment (control gate) disposed above the substrate. Unlike normal transistors, a so-called floating gate is electrically insulated from the substrate and the control gate by insulation layers provided between the substrate and control gate.
To prevent other (adjacent) memory cells from being read out, overwritten and/or erased when a particular memory cell is being read, written on and/or erased, each memory cell includes a second transistor, more specifically a selection transistor, which is formed by a “normal” transistor.
Memory cells of this type can be programmed, read out and erased via the selection, control, bit and source lines. The selection line is connected to a gate portion of the selection transistor. The control line formed by a so-called word line is connected to a control gate of the memory transistor. The bit line is connected to a drain portion of the selection transistor, and the source line is connected to the source portion of the memory transistor.
Via the selection, the control, the bit and the source lines, in the programming, reading and erasing processes, voltages are typically applied to the corresponding (selected) memory cells and the memory cells not to be addressed (not selected). This requires a relatively high voltage at the gate of the selection transistor. This high voltage (needed constantly or frequently) prevents the EEPROM from being capable of being operated with a very low supply voltage, for which there is widespread demand; in any case, it is not possible to lower the supply voltage to below 2.5 V.
Solutions proposed to provide an EEPROM operable with a low supply voltage have resulted in complicated programming procedures that may cause stored information to be lost.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an EEPROM and a method for triggering the EEPROM that overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, in which undesired information losses can be reliably prevented in a simple way and a low supply voltage can be used.
With the foregoing and other objects in view there is provided, in accordance with the invention, an EEPROM, including: a plurality of memory cells each having a memory transistor with a drain terminal and a selection transistor with a source terminal connected in series with the memory transistor; a selection line connected to the selection transistor; a control line connected to the memory transistor; a bit line connected to the drain terminal of the memory transistor; a source line connected to the source terminal of the selection transistor, the plurality of memory cells being programmable, readable and erasable via the selection line, the control line, the bit line and the source line; and a control unit connected to the source line for delivering a programming voltage required for programming the plurality of memory cells via the source line.
It is accordingly provided that the control unit is configured to deliver the programming voltage required for programming the memory cells via the source line.
As a result, it can be attained that the programming voltage is now applied only to the memory transistors of the memory cells that are selected by the associated selection transistor (by the selection line controlling it). Therefore, in programming, no undesired load shift can take place any longer at the memory transistors of unselected memory cells, or more specifically at the floating gates thereof, and as a result the information stored in the memory transistor can be preserved durably in a way that is clearly simple.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an EEPROM and a method for triggering the EEPROM, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
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patent: 5050125 (1991-09-01), Momodomi et al.
patent: 5251171 (1993-10-01), Yamauchi
patent: 5687118 (1997-11-01), Chang
patent: 5706228 (1998-01-01), Chang et al.
patent: 5978265 (1999-11-01), Kirisawa et al.
“A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Onlly Applications”, Wei-Hua Liu et al., Semiconductor Technologies Laboratory, Motorola Inc., Austin Texas, pp. 1-3.
Bloch Martin
Georgakos Georg
Kasprick Kai
Kern Thomas
Peter Jurgen
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Hien
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