EEPROM and logic LSI chip including such EEPROM

Static information storage and retrieval – Floating gate – Particular biasing

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Details

257315, 257316, 257318, 365182, G11C 1140

Patent

active

054652316

ABSTRACT:
Disclosed is an EEPROM cell which can be manufactured with ease by the standard CMOS process. The EEPROM cell of the present invention has a first MOS transistor formed in a semiconductor substrate of a first conductivity type and having current conducting regions of a second conductivity type and a gate electrode, a well of a second conductivity type provided in the substrate, a plate electrode formed on the well with an insulating layer interposed therebetween, and at least one region of the first conductivity type formed in the well adjacent to the plate electrode. The gate electrode and the plate electrode are connected in common and act as a floating gate, and the well acts as a control gate.

REFERENCES:
patent: 4649520 (1987-03-01), Eitan
patent: 4661833 (1987-04-01), Mizutani
patent: 4970565 (1990-11-01), Wu
patent: 5301150 (1994-04-01), Sullivan

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