EEPROM and EEPROM reading method

Details EEPROM and EEPROM reading method EEPROM and EEPROM reading method

1994-08-18

1995-11-14

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518909, 36518911, G11C 1134

Patent

active

054673100

ABSTRACT:
An electrically programmable and electrically erasable non-volatile semiconductor memory device having an array of single transistor cells is provided. The disclosed device protects against reading faults even in the event that adjacent transistors may be over erased. Each of the cell transistor rows has an associated word line and an associated select element. The select elements are connected to the sources of their associated cell transistors and are arranged to activate those cell transistors only when their associated word line is selected. Cell transistors in unselected rows are not activated and thus do not interfere with reading even if they are in an over erased condition.

REFERENCES:
patent: 4366555 (1982-12-01), Hu
patent: 4695979 (1987-09-01), Tuvell et al.
patent: 5097444 (1992-03-01), Fong
IBM Technical Disclosure Bulletin, vol. 27, No. 4B, Sep. 1984, pp. 2726-2729.
IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, "A 23 NS 256K EPROM with Double Layer Metal and Address Transition Detection", Hoff et al., pp. 1250-1258.
1990 Symposium On VLSI Circuits, Jun. 1990, Honolulu, USA, "A 4 MB 5 V Only Flash EEPROM with Sector Erase", Stiegler et al, p. 103-104.

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