Edge-triggered staticized dynamic flip-flop with scan circuitry

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

327211, 327212, 326 98, H03K 19003

Patent

active

058983309

ABSTRACT:
A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage outputs the complement of the scan input signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

REFERENCES:
patent: 5440243 (1995-08-01), Lyon
patent: 5461331 (1995-10-01), Schorn
patent: 5461649 (1995-10-01), Bailey et al.
patent: 5497114 (1996-03-01), Shimozono et al.
patent: 5517136 (1996-05-01), Harris et al.
patent: 5760627 (1998-06-01), Gregor et al.
"Power Saving Latch" IBM Technical Disclosure Bulletin, vol. 39, No. 04, 1996, pp. 65-66, Apr. 1996.
Jiren Yuan and Christer Svensson, "New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings," IEEE Journal of Solid-State Circuits, vol. 31 (No. 1), pp. 62-69 (Jan. 21, 1997).
Neela Bhakta Gaddis et al., "A 56-Entry Instruction Reorder Buffer," pp. 212-213, Digest Of Technical Papers, IEE International Solid-State Circuits Conference, (Feb. 9, 1996).
Hamid Partovi, et al., "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements," Digital Clocks And Latches, IEEE/ISSCC Slide Supplment, pp. 104-105, (Aug. 21, 1996).
Author unknown; "Cascading Dynamic Gates"; CMOS Dynamic Gates; pp. 216-217.
Yuan Ji-Ren, et al., "A True Single-Phase-Clock Dynamic CMOS Circuit Technique," IEEE Journal of Solid-State Circuits, IEEE, vol. 22 (No. 5), pp. 899-900, (Oct. 21, 1987).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Edge-triggered staticized dynamic flip-flop with scan circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Edge-triggered staticized dynamic flip-flop with scan circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Edge-triggered staticized dynamic flip-flop with scan circuitry will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-687868

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.