Edge-triggered staticized dynamic flip-flop with conditional shu

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

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327210, 327211, 327218, 326 98, H03K 3286

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active

059173556

ABSTRACT:
A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

REFERENCES:
patent: 5517136 (1996-05-01), Harris et al.
"Power Saving Latch", IBM Technical Disclosure Bulletin, pp. 65-66, vol. 39, No. 04, Apr. 1996.
Gaddis, N.B. et al., "A 56-Entry Instruction Reorder Buffer", 1996 IEEE International Solid-State Circuits Conference, pp. 212-213, (1996).
Partovi, H. et al., "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements", ISSCC Slide Supplement, p. 104, (1996).
Shoji, Masakazu, CMOS Digital Circuit Technology, Prentice Hall, NJ, pp. 216-217, (1988).
Yuan, Jiren et al., "A True Single-Phase-Clock Dynamic CMOS Circuit Technique", IEEE Journal Of Solid-State Circuits, vol. 22, Oct. 1987, pp. 899-901.
Yuan, Jiren et al., "High-Speed CMOS Circuit Technique", IEEE Journal Of Solid-State Circuits, vol. 24., Feb. 1989, pp. 62-70.

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