Edge triggered set-reset flip-flop (SRFF)

Details Edge triggered set-reset flip-flop (SRFF) Edge triggered set-reset flip-flop (SRFF)

1995-04-28

1997-05-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327 18, 327227, 327294, 327 33, H03K 3355, H03K 3356

Patent

active

056336071

ABSTRACT:
A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second latch.

REFERENCES:
patent: 3509381 (1970-04-01), Marshall, Jr.
patent: 3882325 (1975-05-01), Sakalay
patent: 4300060 (1981-11-01), Yu
patent: 4394769 (1983-07-01), Lull
patent: 4568843 (1986-02-01), Gloanec et al.
patent: 5059818 (1991-10-01), Witt et al.
patent: 5065052 (1991-11-01), Sakagari et al.

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