Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-06-28
2001-04-24
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S198000, C327S212000
Reexamination Certificate
active
06222404
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to circuit storage elements, and more particularly to flip-flops with a dynamic input stage.
2. Description of Related Art
Dynamic flip-flops are widely used in state of the art microprocessors. One particularly advantageous flip-flop that has a dynamic input stage and an output stage is disclosed in commonly owned U.S. Pat. No. 5,825,224, entitled “Edge-Triggered Dual-Rail Dynamic Flip-Flop With Self-Shut-Off Mechanism,” issued to Klass et al. on Oct. 20, 1998, which is incorporated herein by reference in its entirety.
While the flip-flop of U.S. Pat. No. 5,825,224 is a significant advance over prior art configurations, there are certain configurations of the flip-flop that may have a charge-sharing problem. In these configurations, the output signal on one of the output terminals of the dynamic input stages momentarily changes during the evaluation phase. The momentary change may result in a state change on an output terminal of the flip-flop, which in turn can lead to erroneous results.
To better understand the limitations of the prior art flip-flop consider
FIG. 1A
, which is a schematic of a flip-flop
100
according to U.S. Pat. No. 5,825,224. Flip-flop
100
includes a three-input Exclusive OR circuit and a three-input Exclusive NOR circuit that introduce a charge-sharing problem within flip-flop
100
.
In
FIG. 1
, elements with the same reference numeral as the reference number in
FIG. 7
of U.S. Pat. No. 5,825,224 (the '224 patent) are the same element. Therefore, the operation of flip-flop
100
will be apparent to those of skill in the art in view of the description in the '224 patent.
Precharge PMOS transistors
101
to
106
are used to precharge nodes within the Exclusive OR and Exclusive NOR circuit. Precharge PMOS transistors
101
to
106
assure that there is no potential difference across the transistors in the combinatorial logic circuits during the precharge phase. Consequently, in the transition to the evaluation phase there is no spike or false evaluation on the output node that does not change state.
Assume that input signals A, B and C are either all a logic zero, or any two of the signals are a logic one at the start of the evaluation phase. Traces for signals A, B and C are presented in FIG.
1
B. For all these combinations of input signals, the signal on line OUTN
1
remains at a logic one level, while the signal on line OUTN
2
is pulled to a logic zero level as the clock signal on clock line CLK goes active. See FIG.
1
B.
As explained in the '224 patent, two inverter delays after the signal on line OUTN
2
goes inactive, NMOS transistor S
1
is turned off. NMOS transistor S
2
remains turned-on, while keeper NMOS transistor K
1
is turned-off. Consequently, output line OUTN
2
is coupled to the Exclusive NOR circuitry through NMOS transistor S
2
.
If an input signal to the Exclusive NOR circuity changes, e.g., signal A as illustrated in
FIG. 1B
, the output signal of the Exclusive NOR circuitry may change, which in turn momentarily changes the output signal on output line OUTN
2
as illustrated in FIG.
1
B. However, pull-down device
4
prevents the signal on output line OUTN
2
from going to a logic high level. Therefore, the output signal on output line OUTN
2
has at most a momentary glitch
152
that is generated in response to input signal A changing state after the start of the evaluation phase. Momentary glitch
152
may cause a corresponding dip on output terminal/Q.
Flip-flop
100
is used to drive dynamic logic, which typically responds only to a low-to-high transition on a clock edge. Since the downstream dynamic logic driven by the signal on terminal/Q responds to the low-to-high transition on terminal/Q, glitch
152
does not affect the state of the logic. However, in general, in digital logic, glitches are undesirable.
Glitch
152
on line OUTN
2
may be of sufficient magnitude to pass through inverters INV
2
and INV
3
, which in turn causes shut-off transistor S
1
to momentarily conduct. This can result in a low-to-high transition on output terminal Q, which in turn may result in a false evaluation by dynamic logic driven by the signal on output terminal Q. While glitch
152
alone may not be sufficient to cause inverter INV
3
to change state, wire coupling may effectively amplify the glitch so that inverter INV
3
does change state. Consequently, the performance of flip-flop
100
is dependent upon layout conditions combined with input state changes during the evaluation phase.
Consequently, utilization of flip-flop
100
requires an analysis to determine whether layout factors coupled with changes in input signals can result in spurious signals on either of the flip-flops′ two output lines during the evaluation phase. Therefore, a more robust dynamic flip-flop is needed that has performance that is unaffected by input signal changes and layout considerations.
SUMMARY OF THE INVENTION
According to the principles of this invention, a dynamic flip-flop has complete input signal isolation following the hold time in the evaluation phase. A novel shut-off circuit included in the dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce a signal level change on either output terminal during a portion of the evaluation phase following the hold-time.
Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious signals on either input terminal have no affect on the output signal levels. Moreover, the isolation removes concern about cross-coupling between signal lines. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from the precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.
Hence, unlike the prior art flip-flop described above, the dynamic flip-flop of this invention includes all the advantages of the prior art flip-flop and in addition is more robust with respect to charge-sharing problems. Consequently, the dynamic flip-flop of this invention can be used in a wide variety of configurations without requiring an analysis of each configuration to determine whether charge-sharing may be a problem.
In one embodiment, the dynamic flip-flop of this invention includes a first input latch having at least one input line, a clock line, and an output line. The first input latch generates a signal on the output line of the first input latch having a predefined logic state during the first phase of operation. The first input latch generates a signal on the output line of the first input latch in response to the input signal following initiation of the second phase of operation.
The dynamic flip-flop also includes a second input latch having at least one input line, a clock line, and an output line. The second input latch generates a signal on the output line of the second input latch having the predefined logic state during the first phase of operation. The second input latch generates a signal on the output line of the second input latch in response to the input signal following initiation of the second phase of operation.
A shut-off circuit in the dynamic flip-flop of this invention includes a first input line coupled to the output line of the first input latch; a second input line coupled to the output line of the second input latch; and an output line coupled to the first and second input latches. The shut-off circuit generates a signal on the output line in response to a change of signal level on one of the first and second input lines following initiation of the second phase of operation. The output signal from the shut-off circuit decouples the input line of the first input latch from the output line of the first input latch and also simultaneously decouples the input line of the second input latch from the output line of the second input latch for a remainder of the second phase.
Amir Chaim
Das Ashutosh K.
Klass Edgardo F.
Mehta Anup S.
Gunnison Forrest
Gunnison, McKay & Hodgson LLP
Sun Microsystems Inc.
Tran Toan
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