Edge transition detection control of a memory device

Details Edge transition detection control of a memory device Edge transition detection control of a memory device

1997-12-30

1999-11-30

Mai, Son

Static information storage and retrieval

Addressing

Sync/clocking

36518908, 327 36, 327 38, G11C 800

Patent

active

059954442

ABSTRACT:
The pulse width of an internal edge transition detection signal of a memory device is selectably varied by varying the logic state of one or more control signals of the memory device. A number of edge transition detection signals generated by input buffers of the memory device are wire-configured together, such as by a wired-NOR or a wired-NAND configuration, to generate one or more edge transition detection busses. The one or more edge transition detection busses, together with two or more control signals, are introduced to an edge transition detection driver that determines the logic state of a device edge transition detection signal that is generated for use by the entire memory device. Changing the combination of logic states of the control signals allows the pulse width of the device edge transition detection signal to be selectably varied.

REFERENCES:
patent: 5418479 (1995-05-01), Sambandan
patent: 5553033 (1996-09-01), McAdams
patent: 5625604 (1997-04-01), Kim
patent: 5627796 (1997-05-01), Park
patent: 5696463 (1997-12-01), Kwon
patent: 5734282 (1998-03-01), Choi

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