Edge-timing adjustment circuit

Details Edge-timing adjustment circuit Edge-timing adjustment circuit

2008-06-26

2010-02-23

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S166000, C327S170000

Reexamination Certificate

active

07667507

ABSTRACT:
According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner.

REFERENCES:
patent: 5552726 (1996-09-01), Wichman et al.
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6518808 (2003-02-01), Shimoda
patent: 6853225 (2005-02-01), Lee
patent: 7088159 (2006-08-01), Kwak et al.
patent: 7428284 (2008-09-01), Lin
patent: 7598783 (2009-10-01), Shin et al.
patent: 7598784 (2009-10-01), Hunter
patent: 2009/0153202 (2009-06-01), Yagi

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