Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2000-07-26
2002-03-26
Chaudhari, Chandra (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S736000, C257S776000, C257S775000, C438S687000
Reexamination Certificate
active
06362524
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to edge sealing for a semiconductor device, and more particularly, to an improved method for manufacturing an edge seal ring in a copper dual inlaid process, and the device produced thereby.
2. Discussion of the Related Art
The copper dual inlaid or dual damascene process is optimized for the formation of an array of small vias, which connect layers of metal separated by dielectric. With reference to
FIG. 1
, in the formation of such a via, a dielectric layer
20
is provided over a metal layer
22
, and an opening
24
is provided in the dielectric layer
20
exposing a portion of the metal layer
22
. After deposition of a diffusion barrier layer
26
such as tantalum or titanium nitride, copper
28
is deposited over the resulting structure, overfilling the opening
24
and having portions overlying the dielectric layer
20
.
Next, a chemical-mechanical polishing step is undertaken. In such chemical-mechanical polishing process, as is well-known (FIG.
1
), a wafer is mounted on a rotating platen, an independently rotating polishing pad
30
is pressed against the wafer surface
32
, and a slurry
34
carrying small abrasive particles, usually colloidal, is flowed onto the platen. The particles attack and remove small pieces of the wafer surface
32
which are carried away by the movement of the slurry
34
across the surface
32
. Furthermore, a slurry chemistry is selected that dissolves or etches surface materials. The combined actions of the two rotations with the slurry provide for effective chemical-mechanical polishing of the wafer surface
32
, commonly known as planarization.
During such chemical-mechanical polishing, the metal is removed from the dielectric layer
20
and the level of copper
28
A in the opening
24
is generally brought down to the level of the upper surface
36
of the dielectric layer
20
(FIGS.
2
and
3
), so that the resulting upper surface
29
of the copper
28
is substantially coplanar with the upper surface
36
of the dielectric layer
20
, forming an overall substantially planar surface ready for application of the next metal layer thereover.
Typically, the polishing pad
30
is made of somewhat compliant material, so that it is able to form itself generally to the surface
34
to be chemically-mechanically polished, meanwhile providing the greatest pressure on the highest surface area, so that as such polishing proceeds, surface planarity is achieved.
Such a polishing operation has proven effective in the formation of vias, which measure for example 0.2 &mgr;m by 0.2 &mgr;m. In via formation (FIGS.
2
and
3
), the high (projecting) surfaces of the metal on the dielectric layer
20
are chemically-mechanically polished away first. Then, chemical-mechanical polishing proceeds until all metal is removed from the upper surface
36
of the dielectric layer
20
and the upper surface
29
of the copper via
28
A in the opening
24
is generally coplanar with the upper surface
36
of the dielectric layer
20
.
Even though pad
30
has a degree of flexibility, the upper surface
29
of the copper
28
A in the opening
24
is substantially coplanar with the upper surface
36
of the dielectric layer
20
, i.e., “dishing” of the copper (depression at center) is minimal. This is so because of the small dimensions as described above, i.e., the span across which the polishing pad
30
must extend in polishing the copper, from one edge of the dielectric to the other across the opening
24
, is very small, for example 0.2 &mgr;m as stated above.
However, in forming an edge seal ring for a device, i.e., typically a rectangular metal ring around the active area of the device, which metal ring contacts a lower silicon layer to form a seal therewith for keeping contaminants from entering the active area, a significant problem arises. Typically, in the dual inlaid process, the metal ring is formed in the same general manner as are the vias discussed above. That is (FIGS.
4
-
6
), an opening in the form of a rectangular trench
40
is formed in a dielectric layer
42
overlying a silicon layer
44
. The trench
40
surrounds an active device area
46
, and includes four long, straight, continuous trench portions
48
,
50
,
52
,
54
, connected by trench corner regions
56
,
58
,
60
,
62
.
After deposition of a barrier layer
64
over the structure, copper
66
is deposited in the trench
40
and chemical-mechanical polishing is undertaken as described above. A long trench portion
48
with barrier metal
64
and copper
66
therein is shown in
FIGS. 7 and 8
.
During chemical-mechanical polishing, the polishing pad
68
is brought into contact with the exposed surface
70
of the copper
66
, and the higher portions thereof will be removed first. Chemical-mechanical polishing continues until the pad
68
is brought into contact with the edges of the dielectric layer
42
adjacent the trench portion
48
. Because the portion
48
of the trench
40
is quite long, for example, 10 mm, and for example 1 &mgr;m wide, such dimensions, coupled with the compliant nature of the pad
68
, cause a substantial degree of “dishing” or “cupping” to occur in the upper surface
65
of the copper
66
A as shown in FIG.
9
. That is, near the dielectric layer
42
edge adjacent the trench portion
48
(FIG.
10
), the upper surface
65
of the copper
66
and upper surface
43
of the dielectric layer
42
are substantially coplanar, because the pad
68
, even though compliant, is supported in that area by the edge of the dielectric layer
42
. Meanwhile, in the center of the span, distant from the edges of the dielectric layer
42
(FIG.
11
), removal of the copper will be significantly greater. That is, the vertical dimension (thickness) of the copper
66
A above the silicon layer
44
at that point is much less than it is adjacent the dielectric. This lack of planarity can clearly lead to problems during the further fabrication of the device. Furthermore, a trench portion
48
of such significant length has proven difficult to fill with copper
66
as is needed for device reliability.
Therefore, what is needed is a method for forming an edge seal ring in a semiconductor device, which avoids the problem of dishing or cupping of the top surface of the ring during its fabrication, meanwhile being properly functional and promoting device reliability.
SUMMARY OF THE INVENTION
In the present invention, a trench in the general form of a continuous ring is provided in a dielectric layer overlying a silicon layer, the trench defining a continuous opening communicating with the silicon layer. The trench has elongated trench portions connected by trench corner regions. The elongated portions of the trench are each configured to include a plurality of connected legs of substantially the same length, positioned perpendicular to each other. After deposition of a diffusion barrier layer in the trench, metal such as copper or copper alloy is deposited in the trench. A chemical-mechanical polishing step is undertaken. The metal in the trench takes the general form of a continuous ring and is comprised of a plurality of elongated sections connected by corner regions. Each elongated section is made up of a plurality of connected segments, positioned in precise linear (perpendicular in the preferred embodiments) relationship. By forming the ring in short sections, the problem of cupping of the metal during chemical-mechanical polishing is avoided.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the
Blish Richard C.
Greenlaw David C.
Taylor Kurt O.
Chaudhari Chandra
Huynh Yennhu B.
Winters Paul J.
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