Edge seal for a semiconductor device

Details Edge seal for a semiconductor device Edge seal for a semiconductor device

2009-07-08

2011-11-01

Nguyen, Thanh (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

C257S684000, C257S693000, C257S700000, C257SE21545, C257SE23023

Reexamination Certificate

active

08049309

ABSTRACT:
In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

REFERENCES:
patent: 6078068 (2000-06-01), Tamura
patent: 7176524 (2007-02-01), Loechelt et al.
patent: 2004/0026751 (2004-02-01), Makino

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