Image analysis – Image enhancement or restoration – Edge or contour enhancement
Reexamination Certificate
1999-01-27
2002-09-17
Lee, Thomas D. (Department: 2724)
Image analysis
Image enhancement or restoration
Edge or contour enhancement
C382S199000
Reexamination Certificate
active
06453076
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an edge enhancement circuit for enhancing the edge of an image. Specifically, this invention relates to an edge enhancement circuit wherein pixel data used for filter processing for obtaining an edge-enhanced signal are placed at one-pixel intervals with respect to pixel data about a main-line signal to thereby reduce required memory capacity and power consumption.
2. Description of the Related Art
An analog system and a digital system are known as systems for enhancing the contour or edge of an image. In the analog system, a method for separately creating edge-enhanced signals in horizontal and vertical directions and adding these edge-enhanced signals to a main-line signal has heretofore been used. It was however necessary to accurately fit the amounts of delays of the respective signals to one another and perform their adjustments using parts such as delay lines or the like.
In the digital system on the other hand, an edge-enhanced signal added to a certain pixel is determined by calculation from the difference in level between the certain pixel and each pixel lying around the certain pixel. Therefore, edge-enhanced signals including a horizontal direction, a vertical direction and a slanting direction are obtained at a time. Thus, the adjustments for accurately fitting the amounts of delays of the respective signals to one another as in the aforementioned analog system become unnecessary.
FIG. 1
shows a configuration of a digital edge enhancement circuit
100
. The edge enhancement circuit
100
has a signal input terminal
101
to which an analog video signal NVa to be edge-enhanced is inputted, and a clock input terminal
102
to which a clock signal CLK
N
is inputted. When, in this case, the video signal NVa is an NTSC video signal, for example, the frequency of the clock signal CLK
N
is set to 4 fsc (fsc: chrominance sub-carrier frequency).
The edge enhancement circuit
100
also has an A/D converter
103
for sampling the analog video signal NVa, based on the clock signal CLK
N
to thereby obtain a digital video signal NVb, a delay line
104
for delaying the video signal NVb by one horizontal period (1H) to thereby obtain a video signal NVc, and a delay line
105
for further delaying the video signal NVc by one horizontal period (1H) to thereby obtain a video signal NVd. The delay lines
104
and
105
are respectively made up of an FIFO (first-in first-out) memory, for example.
Further, the edge enhancement circuit
100
has a digital filter
106
for performing filter processing using the video signals NVb, NVc and NVd to thereby obtain a digital edge-enhanced signal NIEa. The digital filter
106
performs the following operation to form or create the edge-enhanced signal NIEa. That is,
FIG. 2A
shows nine pixel data (sampled data) used for the operation. P
00
, P
01
and P
02
indicate pixel data constituting the video signal NVd, P
10
, P
11
, and P
12
indicate pixel data constituting the video signal NVc, and P
20
, P
21
, and P
22
indicate pixel data constituting the video signal NVb.
FIG. 2B
shows operators for the respective pixel data. Here, P
11
, becomes a pixel to be noted for obtaining the edge-enhanced signal NIEa. The edge-enhanced signal NIEa with respect to P
11
, is determined from the following equation (1):
NIEa
=8
×P
11
−(P
00
+P
01
+P
02
+P
10
+P
12
+P
20
+P
21
+P
22
) (1)
Moreover, the edge enhancement circuit
100
has a D/A converter
107
for converting the edge-enhanced signal NIEa to an analog signal so as to obtain an analog edge-enhanced signal NIEb, a D/A converter
108
for converting the video signal NVc outputted from the delay line
104
to an analog signal as a main-line signal so as to obtain an analog video signal NVe, an adder
109
for adding the edge-enhanced signal NIEb to the video signal NVe to thereby obtain an edge-enhanced analog video signal NVf, and a signal output terminal
110
for outputting the video signal NVf therefrom.
Incidentally, the delay lines
104
and
105
, the digital filter
106
, and the D/A converters
107
and
108
are supplied with the clock signal CLK
N
as an operating clock.
The operation of the edge enhancement circuit
100
shown in
FIG. 1
will be described.
The analog video signal NVa inputted to the signal input terminal
101
is supplied to the A/D converter
103
where it is sampled based on the clock CLK
N
so as to be converted to the digital video signal NVb. The video signal NVb is delayed by one horizontal period by the delay line
104
to obtain the video signal NVc. The video signal NVc is further delayed by one horizontal period by the delay line
105
to obtain the video signal NVd. These video signals NVb through NVd are supplied to the digital filter
106
where the filter processing using the video signals NVb through NVd is performed to form the digital edge-enhanced signal NIEa.
Further, the video signal NVc outputted from the delay line
104
is supplied to the D/A converter
108
where it is converted to the analog signal, whereby the analog video signal NVe is obtained as the main-line signal. Similarly, the edge-enhanced signal NIEa outputted from the filter
106
is supplied to the D/A converter
107
where it is converted to the analog signal, whereby the analog edge-enhanced signal NIEb is obtained. Further, the video signal NVe and the edge-enhanced signal NIEb are supplied to the adder
109
where they are added together to obtain the edge-enhanced analog video signal NVf. The resultant video signal NVf is drawn from the adder
109
to the signal output terminal
110
.
Since the frequency of the clock signal CLK
N
is low when the analog video signal NVa inputted to the signal input terminal
101
is an ordinary video signal such as an NTSC video signal or the like, the edge enhancement circuit
100
shown in
FIG. 1
offers no problem. However, the edge enhancement circuit has a drawback in that when the analog video signal NVa is a hi-vision video signal, the frequency of the clock signal CLK
N
becomes high to increase the capacity of the FIFO memory constituting each of the delay lines
104
and
105
, and since the basic clock used for the computation of the digital filter
106
becomes high-speed, power consumption greatly increases. When a hi-vision signal having 2200 pixels/line, for example, is edge-enhanced, the frequency of the clock signal CLK
N
results in 74.25 MHz. Further, the FIFO memory constituting each of the delay lines
104
and
105
needs a capacity of 2200 words ×8 bits per one (with the quantization of the A/D converter and D/A converter being performed as 8 bits) and an access speed of about 10 ns.
SUMMARY OF THE INVENTION
With the foregoing in view, it is therefore an object of the present invention to provide an edge enhancement circuit capable of reducing required memory capacity and power consumption when, for example, a hi-vision signal is edge-enhanced.
According to one aspect of the invention, for achieving the above object, there is provided an edge enhancement circuit, comprising first analog/digital converting means for sampling an input analog video signal, based on a first clock signal to thereby obtain a first digital video signal, filter processing means for filter-processing the first digital video signal to thereby obtain a digital edge-enhanced signal, second analog/digital converting means for sampling the input analog video signal, based on a second clock signal identical in frequency to the first clock signal and kept in inverse phase with each other to thereby obtain a second digital video signal, switch means for alternately taking out pixel data (sampled data) constituting the first and second digital video signals, based on a third clock signal having a frequency corresponding to twice that of the first clock signal to thereby obtain a digital main-line signal, and signal adding means for adding the signal outputted from the filter processing means
Brinich Stephen
Frommer William S.
Frommer & Lawrence & Haug LLP
Lee Thomas D.
Sony Corporation
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