Edge channel FET

Details Edge channel FET Edge channel FET

1984-12-19

1986-10-28

Edlow, Martin H.

357 15, 357 56, 357 4, H01L 4902

Patent

active

046202072

ABSTRACT:
Edge channel FET structural geometry and processing is disclosed. A plurality of mesa stacked horizontal layers are provided including source and drain semiconductor layers (74, 76) separated by an insulator layer (75) and having exposed edges (78, 80) at a generally vertical side (83) of the mesa. A generally vertical semiconductor layer (84) extends along the side of the mesa over the exposed source and drain layer edges and forms a channel (93). A gate layer (91, 92) on the channel controls depletion region spreading in the channel layer to control conduction therethrough between the source and drain layers. Channel length is extremely small, as low as 0.1 micron. Ohmic contacts (87, 90) to the source and drain layers are defined several microns away from the conducting channel, resulting in considerable reduction in fabrication complexity, as well as improved reliability. Fabrication and alignment of the gate to the active channel layer is simplified.

REFERENCES:
patent: 3893155 (1975-07-01), Ogiue
patent: 4007297 (1977-02-01), Robinson et al.
patent: 4098921 (1978-07-01), Calviello
patent: 4212022 (1980-07-01), Beneking
patent: 4466008 (1984-08-01), Beneking
patent: 4543320 (1985-09-01), Vijan
patent: 4547789 (1985-10-01), Cannella et al.

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