Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-08-23
2001-07-31
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S041000, C451S397000
Reexamination Certificate
active
06267649
ABSTRACT:
BACKGROUNG OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of polishing the edge of a wafer on which copper has been deposited by using a contour-shaped pad.
(2) Description of the Prior Art
Chemical Mechanical Polishing is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may include abrasive materials therein, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
The profile of the polishing pad plays an important role in determining good overall polishing results. The polishing pad can, for instance, be profiled thick at the inner diameter of the polishing pad as compared to the outer diameter of the polishing pad and visa versa. The profile of the polishing pad is typically achieved by trial and error and by adjusting the position of a diamond dresser. This method of profiling the polishing pad is destructive, time consuming and causes the loss of the polishing pad. Since this measure of the polishing pad profile can only be performed at the end of the useful life of the polishing pad, the wrong profile can only be detected after the polishing pad has served its useful life.
A polishing pad is typically fabricated from a polyurethane and/or polyester base material. Pads can for instance be specified as being made of a microporous blown polyurethane material having a planar surface and a Shore D hardness of greater than 35 (a hard pad). Other materials used for polishing pads are foam polyurethane, sueded foam polyurathene, unwoven fabric, resin-impregnated unwoven fabric. Semiconductor polishing pads are commercially available such as models IC1000 or Scuba IV of a woven polyurethane material.
One factor, which contributes to the unpredictability and non-uniformity of the polishing rate of the CMP process, is the non-homogeneous replenishment of slurry at the surface of the substrate and the polishing pad. The slurry is primarily used to enhance the rate at which selected materials are removed from the substrate surface. As a fixed volume of slurry in contact with the substrate reacts with the selected materials on the surface of the substrate, this fixed volume of slurry becomes less reactive and the polishing enhancing characteristics of that fixed volume of slurry is significantly reduced. One approach to overcoming this problem is to continuously provide fresh slurry onto the polishing pad. Slurry typically includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles.
This approach presents at least two problems. Because of the physical configuration of the polishing apparatus, introducing fresh slurry into the area of contact between the substrate and the polishing pad is difficult. Providing a fresh supply of slurry to all positions of the substrate is even more difficult. As a result, the uniformity and the overall rate of polishing are significantly affected as the slurry reacts with the substrate.
In the art of fabricating semiconductors, it is important that the surface of a semiconductor wafer be planar in order to meet the requirements of optical projection lithography. The assurance of planarity is crucial to the lithography process, as consistent and uniform depth of focus of the lithography process across a surface is often inadequate for surfaces that do not have good planarity.
During the fabrication of VLSI and ULSI semiconductor wafers, it is also critically important to use wafers that are free of any surface Cu
+
or Cu
++
ions since the presence of these impurities has a direct and negative effect on device yield and throughput. It is therefore of extreme importance to use effective means for the control and removal of these impurities from the surface of the wafer since these impurities may, during further high temperature processing steps, diffuse into the wafer surface thereby substantially altering the chemical composition of the wafer. In addition, impurities can be classified as donor or acceptor dopants; these dopants will have an impact on the performance of subsequently produced semiconductor devices. Yet other impurities may cause surface dislocations or internal stacking misalignments or faults further having a negative impact on semiconductor manufacturing yield and cost. It is therefore clear that an effective method must be available to thoroughly clean the surface of the semiconductor substrate from all impurities while this process of removal may have to be repeated at various intervals during the complete processing sequence.
In the conventional approach, the wafer is held in a circular carrier, which rotates. The polishing pads, made from a synthetic fabric, are mounted on a polishing platen which has a flat surface and which rotates. The rotating wafer is brought into physical contact with the rotating polishing pad; this action constitutes the Chemical Mechanical Polishing process. Slurry, which typically includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles, is dispensed onto the polishing pad typically using a peristaltic pump. The excess slurry typically goes to a drain, which means that the conventional CMP process has an open loop slurry flow and therefore may use and dispense with an excessive amount of slurry that may add significantly to the processing cost. During this process of polishing, rate of slurry flow must also be exactly controlled.
One of the techniques of removing surface layers from the surface of a substrate is the method of lapping. For this method, a work surface is pressed against a rotating plate, typically made of a metal, while slurry of abrasive material is passed between the work surface and the plate. Double lapping can be accomplished by pressing the substrate between two rotating plates that rotate in opposite directions. While the process applied during lapping strongly resembles the process of the conventional CMP, the severity of the abrasive action between the work surface and the rotating plates can result in deep micro-fissures in the piece of the work surface. These micro-fissures or cracks need to be further removed (by chemical etching and polishing) before the surface of the wafer becomes of acceptable quality.
The process of polishing a wafer surface also requires that the work surface be pressed against a rotating pad while abrasive slurry is fed between the work surface and the pad. Polishing is frequently used in applications where, in applying the CMP process to Intra-Level Dielectric (ILD) and Inter Metal Dielectric (IMD) that are used for the manufacturing of semiconductor wafers, surface imperfections (micro-scratch) present a problem. Imperfections caused by micro-scratches in the ILD and IMD can range from 100 to 1000 EA for 200 mm. wafers, where an imperfection typically has a depth from 500 to 900 Å and a width of from 1000 to 3000 Å
0
. As part of the polishing process of the ILD and IMD, a tungsten film is deposited; the surface imperfections will be filled with tungsten during this deposition. For devices within the semiconductor wafer with a dimension of 0.35 um or larger, an etching process is used where the tungsten that has entered the imperfections within the wafer surface can be removed. For the larger size devices within the semiconductor wafer there is therefore no negative impact on the yield of
Chiou Hung-Wen
Lai Han-Chung
Ackerman Stephen B.
Hail III Joseph J.
Industrial Technology Research Institute
Ojini Anthony
Saile George O.
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